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Trick QUIZ

What do these bits represent?

1101 1110

Trick QUIZ

What do these bits represent?

1101 1110

Unsigned integer: …

Signed integer (2’s complement): …

Fixed-point fraction

IBM 437 character: …

Latin-1 character: …

14 bits: …

IEEE-754 on 32 bits: …

IEEE-754 on 64 bits: …

QUIZ Select all that apply:

The Latin-1 character set:

• Is a 5-bit representation

• Is an extension of ASCII

• Is an extension of Unicode

• Contains letters used in European languages

QUIZ Select all that apply:

The Unicode representation:

• Uses 16 bits

• Is an extension of ASCII

• Is an extension of Latin-1

• Is an extension of IBM-437

• Contains letters used in all world languages

• Can accommodate over 65,000 characters

• Is used in the majority of web pages today4 EOL4

Your boss tells you to develop a webpage

using the extended ASCII character set.

What do you reply?

Chapter 3

REVIEW of Boolean Algebra

and Digital Logic

Name the Boolean functions and draw the gates:

QUIZ: Boolean Algebra

Draw the truth table for the Boolean function:

Complete the Boolean identities:

Use Boolean identities to simplify:

• Sometimes it is more economical to build a

circuit using the complement of a function (and

complementing its result) than it is to implement

the function directly.

• DeMorgan’s law provides an easy way of finding

the complement of a Boolean function.

• Recall DeMorgan’s law states:

3.2 Boolean Algebra

• DeMorgan’s law can be extended to any number of

variables.

• Replace each variable by its complement and

change all ANDs to ORs and all ORs to ANDs.

• Thus, we find the the complement of:

3.2 Boolean Algebra

• Through our exercises in simplifying Boolean

expressions, we see that there are numerous

ways of stating the same Boolean expression.

– These “synonymous” forms are logically equivalent.

– Logically equivalent expressions have identical truth

tables.

• In order to eliminate as much confusion as

possible, designers express Boolean functions in

standardized or canonical form.

3.2 Boolean Algebra

• There are two canonical forms for Boolean

expressions: sum-of-products and product-of-sums.

– Recall the Boolean product is the AND operation and the

Boolean sum is the OR operation.

• In the sum-of-products form, ANDed variables are

ORed together.

– For example:

• In the product-of-sums form, ORed variables are

ANDed together:

– For example:

SOP and POS

Write the SOP (sum-of-products) form and

the gate diagram:

Write the SOP (sum-of-products) form and

the gate diagram:

• We have looked at Boolean functions in abstract

terms.

• In this section, we see that Boolean functions are

implemented in digital computer circuits called gates.

• A gate is an electronic device that produces a result

based on two or more input values.

– In reality, gates consist of one to six transistors, but digital

designers think of them as a single unit.

– Integrated circuits contain collections of gates suited to a

particular purpose.

3.3 Logic Gates

• The three simplest gates are the AND, OR, and NOT

gates.

• They correspond directly to their respective Boolean

operations, as you can see by their truth tables.

3.3 Logic Gates

• Another very useful gate is the exclusive OR

(XOR) gate.

• The output of the XOR operation is true only when

the values of the inputs differ.

Note the special symbol

for the XOR operation.

3.3 Logic Gates

Use DeMorgan to prove that the circuit below

implements the XOR gate:

Image source: Wikipedia →XOR gate

• NAND and NOR

are two very

important gates.

Their symbols and

truth tables are

shown at the right.

3.3 Logic Gates

• NAND and NOR

are known as

universal gates

because they are

inexpensive to

manufacture and

any Boolean

function can be

constructed using

only NAND or only

NOR gates.

3.3 Logic Gates

Gates can have multiple inputs and multiple

outputs.

• E.g., a second output can be provided for

the complement of the operation.

3.3 Logic Gates

• The main thing to remember is that combinations

of gates implement Boolean functions.

• The circuit below implements the Boolean

function:

We simplify our Boolean expressions so

that we can create simpler circuits.

3.3 Logic Gates

3.4 Integrated Circuits (IC)

Problem: Design a circuit using the SSI IC 7400

(Quad NAND)Small Scale Integrated

Integrated Circuits (IC)

Problem: Design a circuit using the SSI IC 7400

3.5 Combinational Circuits

• We have designed a circuit that implements the

Boolean function:

• This circuit is an example of a combinational logic

circuit.

• Combinational logic circuits produce a specified

output (almost) at the instant when input values

are applied.

– In a later section, we will explore circuits where this is

not the case.

• Combinational logic circuits

give us many useful devices.

• One of the simplest is the

half adder, which finds the

sum of two bits.

• We can gain some insight as

to the construction of a half

adder by looking at its truth

table, shown at the right.

Combinational Circuits

• As we see, the sum can be

found using the XOR

operation and the carry

using the AND operation.

• We can change our half

adder into to a full adder

by including gates for

processing the carry bit.

• The truth table for a full

adder is shown at the

right.

• How can we change the

half adder shown below

to make it a full adder?

• Here’s our completed full adder.

• Just as we combined half adders to make a full

adder, full adders can connected in series.

• The carry bit “ripples” from one adder to the next;

hence, this configuration is called a ripple-carry

adder.

Today’s systems employ more efficient adders.

To do in notebook for next time:

-Read and take notes: pp.137-158

(stop before Example 3.1.3 – Decoder)

-End-of-chapter Exercises 1, 2, 3, 4, 22

Draw the truth table for a XOR gate:

Find the SOP expression for a XOR gate:

Find the Boolean

expression for the

following circuit:

Find the Boolean

expression for the

following circuit:

Cout = ( ) + ( )

Sum = ( ) ( )

Design the Full Adder directly, based on the truth table,

using SOP. Compare to the previous design.

QUIZ: Combinational Circuits

Minimize the FA using K-maps.

Use the following layout for each output:

QUIZ: Combinational Circuits

FA solution

Which implementation is best?

(Trick question!)

• Among other things, they are useful in selecting a

memory location according to a binary value placed

on the address lines of a memory bus.

• Address decoders with n inputs can select any of 2n

locations.

Decoders

2-to-4 decoder implementation. Each AND gate

generates a minterm!

If x = 0 and y = 1,

which output line

is enabled?

Decoders

Draw the gate diagram for a 3-to-8 decoder,

with inputs x, y, z.

QUIZ: Decoders

We’re designing a computer with 64 KB of RAM.

How many address bits are needed?

Typical decoder application:

memory addressing circuit

Each individual

Byte must be

addressed

individually!

Note: this is different from the MARIE computer, in which each memory location has

two Bytes!

From cost analysis, it turns out that the cheapest

solution uses 8-KB RAM chips.

How many chips are needed?

How many address bits does each chip accept?

How many address bits are needed to distinguish

among the chips?

We implement it with 8 RAM chips, having 8KB each.

The 3 MSB are used to distinguish among the chips.

Write in hex the address range for each of the chips.

• A multiplexer is the opposite

of a decoder.

• It selects a single output

from several inputs.

• The particular input chosen

for output is determined by

the value of the multiplexer’s

control lines.

• To be able to select among n

inputs, log2n control lines are

needed.

Multiplexers

Implementation of a 4-to-1 multiplexer.

Each input is validated by a minterm!

If S0 = 1 and S1 = 0,

which input is

transferred to the

output?

This shifter

moves the bits

of a nibble one

position to the

left or right.

If S = 0, in which

direction do the

input bits shift?

Shifters

Draw the block

diagram of this

shifter.

QUIZ: Shifters

2-bit ALU

Draw a simplified

diagram of the

ALU when both f

inputs are zero:

f1f0 = 0 0

2-bit ALU

Draw a simplified

diagram of the

ALU when :

f1f0 = 0 1

2-bit ALU

Draw a simplified

diagram of the

ALU when :

f1f0 = 0 1

2-bit OR

2-bit ALU

Draw a simplified

diagram of the

ALU when :

f1f0 = 1 0

2-bit ALU

Draw a simplified

diagram of the

ALU when :

f1f0 = 1 1

2-bit ALU

Conclusion ?

Individual work for next time

• Read pages 157-162 , and 199-208 (“Focus

on K-maps”)

• Solve in notebook:

– Ex. 48, 49 on p.195

– Ex. 1, 2 on p.209

3.6 Sequential Circuits

• Combinational logic circuits are perfect for

situations when we require the immediate

application of a Boolean function to a set of inputs.

• There are other times, however, when we need a

circuit to change its value with consideration to its

current state as well as its inputs.

– These circuits have to “remember” their current state; they

have memory

• Sequential logic circuits provide this functionality.

To retain their state values, sequential circuits rely

on feedback.

• Example:

– If Q is 0 it will always be 0, if it is 1, it will always be 1.

In asynchronous sequential circuits (a.k.a. latches),

state changes occur whenever the inputs change.

In synchronous sequential circuits (a.k.a. flip-flops),

state changes are controlled by clocks.

• A “clock” is a special circuit that sends electrical

pulses through a circuit.

• Clocks produce “square” electrical waveforms:

• Synchronously: on the rising edge/falling edge,

a.k.a. edge-triggered

• Asynchronously: when the clock pulse is at its

highest/lowest voltage, a.k.a. level-triggered

Sequential Circuits can change state:

You can see how feedback works by examining the

most basic sequential logic components, the SR

latch and flip-flop.

– The “SR” stands for set/reset.

The behavior of an SR latch is described by a

characteristic table:

• Q(t) means the value of the output at time t

• Q(t+1) is the value of Q after the next clock

pulse.

SR latch

QUIZ: Analyzing sequential circuits

What exactly does “undefined” mean here?

• To draw a truth table,

note that the SR flip-flop

actually has three inputs:

S, R, and its current

output, Q.

• Notice the two undefined

values. When both S and

R are 1, the SR flip-flop is

unstable (well, it’s a little

more complicated … see

Digital)

SR latch

QUIZ: Analyzing sequential circuits

Derive the characteristic table for this circuit

Clocked SR latch

Changes can

occur only on the

positive level of

Text calls it

flip-flop

SKIP JK flip-flop

The D flip-flop is the fundamental circuit of

computer memory

D flip-flop

QUIZ: Problem 55/196

• The behavior of sequential circuits can be

expressed using characteristic tables or finite state

machines (FSMs).– FSMs consist of a set of nodes that hold the states of the

machine and a set of arcs that connect the states.

• Moore and Mealy machines are two types of FSMs

that are equivalent.– They differ only in how they express the outputs of the

machine.

• Moore machines place outputs on each node, while

Mealy machines present their outputs on the

transitions.

Moore machine

Mealy machine

Moore vs. Mealy

Moore and Mealy machines are equivalent, i.e. they can be

used to implement circuits with the same behavior, but …

• Moore may need more states than Mealy

• Mealy may need more combinational logic than Moore

QUIZ: Design

Draw the FSM diagram for a Moore machine

• Has one input and one output

• Turns its output to 1 if and only if at the

previous 3 clock “ticks” the input has been

QUIZ: Analysis

Draw the characteristic table and the FSM diagram

for this circuit.

What function does it perform?

We can trade off flip-flops (memory) for (combinational)

logic: here is the same 4-state counter in the “walking ring”

implementation

QUIZ: If using ICs from the 7400 family, which

implementation requires fewer units?

7400 - quad inverter

7486 - quad XOR

7474 - double D w/positive and negative outputs Q

74174 - hex D w/positive outputs Q

74175 - quad D w/positive and negative outputs Q

Individual work for next time

• Read pages 162-170

• Solve in notebook:

– Ex. 52 p.196

94EOL 3

QUIZ: Design

Draw the FSM diagram for a Moore machine

• Has two inputs (x, y) and one output (z).

• Turns its output to 1 if and only if at the

previous 2 clock “ticks” the inputs have

been identical.

QUIZ: Analysis Problem 52/196

QUIZ: Problem 52/196

Explain in your own words the

functionality of this circuit.Hint: Consider separately the case X = 0 and X = 1.

• It is difficult to express the complexities of actual

implementations using only Moore and Mealy

machines.– For one thing, they do not address the intricacies of

timing very well.

– Secondly, it is often the case that an interaction of

numerous signals is required to advance a machine from

one state to the next.

• For these reasons, Christopher Clare invented the

algorithmic state machine (ASM).

The next slide illustrates the components of an ASM.

Algorithmic State Machines

Moore-type outputs

Mealy-type outputs

Where are the Moore and Mealy outputs?

ASM for a microwave oven

3.6.5 Examples of

Important Sequential

Circuits

SKIP: Hardware-free machines

4-bit register with D flip-flops

Real-life registers also have CLEAR

and ENABLE/WRITE inputs

They can also SHIFT or ROTATE their

bits (Left or Right)

4-bit binary counters(Use the D version, not the JK given in text!)

Source: http://teahlab.com/4-bit_counter_modulo-16_D_flipflop/

But note that the JK circuit needs less combinational logic!

Source: http://teahlab.com/4-bit_counter_modulo-16_D_flipflop/

QUIZ: Assume the counter is in state ‘7’ right

before the positive edge of CLK.

Write the states of all

signals in the diagram.

Then write the states

of all signals after the

positive edge.

handout

Small Memory Circuit: four 3-bit words

QUIZ: Write the integer 6 in Word 1handout

Convolutional coding is performed on a string of bits

arriving in real-time (e.g. digital video, digital

telephony, satellite links, reading tape and disk)

The output bit is a function of the current and

previous input bits, therefore we need memory,

i.e. sequential circuits

Convolutional Coders and Decoders

Do you recognize

this combinational

circuit?

Do you recognize

this sequential

circuit?

Convolutional Coders and Decoders

Frequency divider

Back to digital analysis: What is the output Q of this circuit?

Conclusion: Q and Q’ have

double the periof (half the

frequency) of Clock.

Conclusion: During each cycle

of Clock, a different bit is

created at the output.

Conclusion:

• The flip-flops are driven at half the frequency (i.e.

double the period) of the original CLOCK

• Two bits are output for every one bit input:

– A C from the top AND gate

– A B C from the bottom AND gate

Called (2,1)

convolutional

• It is a particular (2,1) convolutional code

• It is used to convert the (weak, noisy) analog

signal from the head of a magnetic disk or tape

drive into a digital signal.

• You can find more details on PRML at the end of

Chapter 2 (Section 2A.6 - p.134).

Partial Response Maximum Likelihood

Fig. 3.34 + explanations on p.180

→ Read and understand the operation of the PRML

encoder!

Initially all FFs

store 0s (RESET)

First bitSecond bitThird bit

Fig. 3.34 – Why are there two zeros at the beginning?

This is the beginning

Continue the

analysis in Fig. 3.34

PRML encoder characteristic table

Note: Although the circuit has 3 FFs, the state is defined based on only two!

Extra-credit

PRML encoder FSM

Moore or Mealy?

F(1101 0010)=11 01 01 00 10 11 11 10

Starting in state 0,

the encoder receives

the bits shown (from

left to right):

PRML encoding example

F(0100 1111) =

Use the FSM diagram

to encode:

0100 1111

(starting in state 0)

QUIZ: PRML encoding

Decoding is achieved by inverting the inputs and outputs

of the encoder Mealy machine:

PRML decoding

F(11 01 01 00 10 11 11 10) = 1101 0010

We can see from the

decoder FSM that, if no

errors have occurred,

the decoded sequence

matches the one

encoded in the previous

example:

PRML decoding

F(11 01 01 10 10 11 11 10) = 110? ????

What if there are

errors?

Example:

PRML decoding

What is the state of the decoder

when this pair of bits arrives?

F(11 01 01 00 10 11 11 10) = 1101 0010

The fact that there is a

limited set of possible

state transitions in the

encoding process is

crucial to the error

control capabilities of

PRML encoding example

Error control

Error detection Error correction

F(11 01 01 10 10 11 11 10) = 110? ????

Conclusion: The error

is detected … but this is

not enough!

The decoder has to

be able to recover and

keep churning out the

PRML decoding

F(11 01 01 00 10 11 11 10) = 1101 0010

F(11 01 01 10 10 11 11 10) = 110? ????

Solution:

Minimize the total error of the

sequence of bits that starts w/the error!

F(11 01 01 00 10 11 11 10) = 1101 0010

“PR”

“ML”

PRML decodingPartial Response, Max. Likelihood

F(11 01 01 10 10 11 11 10) = 110? ????

Solution:

Minimize the total error of the

sequence of bits that starts w/the error!

PRML decodingPartial Response, Max. Likelihood

F(11 01 01 00 10 11 11 10) = 1101 0010

“PR”

“ML”

How long a sequence?

From an error-correction standpoint, the longer

the better …

… but longer sequences mean:

• longer decoding delay

• heavier computational load (CPU cycles and

memory)

In this example we use a sequence of 4 pairs

PRML decoding

F(00 10 11 11) = 1001

A more intuitive way of

understanding the

decoding process is

through a lattice,

famously known as

trellis diagram.

This is the trellis diagram

for the correct sequence

starting in state 1

Decoding PRML with Trellis diagrams

F(10 10 11 11) = ????

This is the diagram for

the incorrect sequence

starting in state 1.

In the circles we have

the accumulated

(Hamming) errors.

The path of least error

outputs 1001, thus 1001 is

the string of maximum

likelihood (ML).

F(00 10 11 11) = 1001

F(10 10 11 11) = 1001

Decoding PRML with Trellis diagrams

F(11 11 01 00 10 11 11 10) = 1??? ????

Draw the trellis diagram and

work the ML sequence for the

error below.

Hints:

• What state is the decoder in

when the error is

encountered?

• For simplicity, use a sequence

length of only three pairs.

QUIZ: Trellis decoding

F(11 11 01 00 10 11 11 10) = 1??? ????

QUIZ: Trellis decoding

Homework for Ch.3

End of chapter exercises

6, 23, 37, 43, 58, 65

Due next Tuesday at the beginning of class,

but strongly recommended as preparation for

next week’s midterm!

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