TMS320TMS320C6xxC6xxDr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004

ArchitecturArchitecturee

C6xx

2

'C6x'C6x - - System Block System Block DiagramDiagram

PPEERRIIPPHHEERRAALLSS

On ChipOn Chip Ex. MemoryEx. Memory

Internal BusesInternal BusesOff ChipOff Chip

Ex. MemoryEx. Memory

CPUCPU

.D1.D1

.M1.M1

.L1.L1

.S1.S1

.D2.D2

.M2.M2

.L2.L2

.S2.S2

Regs (B

0-B15)

Regs (B

0-B15)

Regs (A

0-A15)

Regs (A

0-A15)

Control Regs Control Regs

Harvard

PC

3

‘‘C6xC6x - - Internal BusesInternal Buses

VLIWVLIW

ReadRead

WriteWrite

CPU

DMA

4

'C6x'C6x - - System Block System Block DiagramDiagram

32/6432/64

256

32/64

32/6432/64

32

I/O

Mappatein memoria

Mappatein memoria

5

'C6x'C6x - - PeripheralsPeripherals

On ChipOn Chip

Off ChipOff ChipEach of these peripherals has a module dedicated

to them and each of these can exist on the C6x

6

EMIFEMIFclk1

clk2

clk3

Ad1

Ad2

Ad3clk0

7

Memory SizeMemory Size per deviceper device

DevicesDevices InternalInternal EMIF AEMIF A EMIF BEMIF B

C6201, C6701C6204, C6205

P = 64 kBD = 64 kB

52M Bytes (32-bits wide)

N/AC6202 P = 256 kB

D = 128 kB

C6203 P = 384 kBD = 512 kB

C6211C6711 L1P = 4 kB

L1D = 4 kBL2 = 64 kB

128M Bytes (32-bits wide)

N/A

C671264M Bytes (16-bits wide)

C6713L1P = 4 kBL1D = 4 kBL2 = 256 kB

128M Bytes (32 - bits wide) N/A

C6411DM642

L1P = 16 kBL1D = 16 kBL2 = 256 kB

128M Bytes (32-bits wide) N/A

C6414C6415C6416

L1P = 16 kBL1D = 16 kBL2 = 1 MB

256M Bytes (64-bits wide)

64M Bytes (16-bits wide)

HARVARD Off Chip Memory

SlowFast

8

HPIHPI / / XBUSXBUS / / PCIPCI

9

McMcBBSPSP//AASPSP and and UtopiaUtopia

Bus I2C: Protocollo Seriale Sincrono (due linee bidirezionali, clock e dati sincroni, più la massa)ATM: Asynchronous Transfer Mode

10

GPIOGPIO

• LED• SWITCH

11

DMADMA / / EEDMADMA

12

TimerTimer / / CounterCounter

13

EthernetEthernet

14

Video PortsVideo Ports

15

VVCPCP / / TTCPCP - - 3G Wireless3G Wireless

16

Phase Locked LoopPhase Locked Loop ( (PLLPLL))

17

Clock CycleClock Cycle

x8

18

CC67136713 Architecture Architecture

19

CC67136713-DSK-DSK Architecture Architecture

20

CPLDsCPLDs

21

CC64166416ArchitectureArchitecture

22

CC64166416-DSK-DSK Architecture Architecture

Slow

Fast

23

‘‘C6xC6x - - Family Part Family Part NumberingNumbering

Ex = TMS320 L C6 2 01 PKG A 200

TMS320 = TI DSP L = Place holder for

voltage levels C6 = C6x family 2 = Fixed/Floating-point

core 01 = Memory/peripheral

configuration PKG = Pkg designator (actual

letters TBD) A = -40 to 85C (blank for

0 to 70C) 200 = Core CPU speed in

Mhz

24

ArchitectureArchitecture

Links:Links: C6711 data sheet: C6711 data sheet: tms320c6711.pdftms320c6711.pdf C6713 data sheet: C6713 data sheet: tms320c6713.pdftms320c6713.pdf C6416 data sheet: C6416 data sheet: tms320c6416.pdftms320c6416.pdf User guide C6xx: User guide C6xx: spru189f.pdfspru189f.pdf Errata: Errata: sprz173c.pdfsprz173c.pdf