TIMING DIAGRAMS

Richa Upadhyay Prabhu

NMIMS’s MPSTME

richa.upadhyay@nmims.edu

January 19, 2016

Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, 2016 1 / 21

MACHINE CYCLE or BUS CYCLE or INSTRUCTIONCYCLE

Definition: one discrete information transfer on busAlso defined as time taken by processor to execute an instruction

Typically, all processor utilizes the following 5 stage cycles:

Fetch instruction from main memory

Decode the instruction

Fetch data from main memory

Execute Instruction

Store result

Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, 2016 2 / 21

MACHINE CYCLE or BUS CYCLE or INSTRUCTIONCYCLE

All these operations are performed w.r.t. CLOCK

Microprocessor performs an operation in a specific time period i.e.specific clock cycles known as T-state

T-state is time period of a single cycle of the clock frequency

Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, 2016 3 / 21

MACHINE CYCLE

No. of T-state required to access a peripheral is called MACHINECYCLE

Access a peripheral means to perform a read or a write operationeither from memory or an I/O In 8086 Memory read or memory writerequire 4 T-states.

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Timing Diagram for a read cycle

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Timing Diagram for a read cycle

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Timing Diagram for a read cycle

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Timing Diagram for a read cycle

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Timing Diagram for a read cycle

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Timing Diagram for a read cycle

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Timing Diagram for a read cycle

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Timing Diagram for a read cycle

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Timing Diagram for a read cycle

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Timing Diagram for a read cycle

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Timing Diagram for a read cycle

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Timing Diagram for a read cycle

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Timing Diagram for a read cycle

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Timing Diagram for a read cycle

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Timing Diagram for a read cycle

Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, 2016 19 / 21

Timing Diagram for a read cycle

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Timing Diagram for a read cycle

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