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Test Circuit for Locating Open Leads of QFP ICs

M.Hashizume, A.Shimoura,

M.Ichimiya, H.Yotsuyanagi

The Univ. of Tokushima, JAPAN

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Outline

1. Background

2. Our targeted problem:

=open lead location of CMOS QFP ICs

3. Our test method

4. Our test circuit and the design method

5. Feasibility of test circuit design

6. Conclusion

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BackgroundMany logic circuits are implemented with fine-pitch QFP ICs

and a PCB of fine line layout.

(ex.)circuits that downsizing and high performance are not requested strongly

Open leads of QFP ICs occur more frequently in soldering process.

[Targeted Defects] Open lead of QFP ICs occurring in soldering process

open lead

solder bridging

peeling-off pattern

pattern short

Now, 0.4mm

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Our Targeted Problem Our targeted tests: Tests in subcontract soldering factories

CUTs: circuit s made of QFP ICs in which downsizing and high performance are not requested strongly

Difficulty:

o Boundary scan technology may not be introduced in QFP ICs.

o Test vectors are provided from ordering manufactures and can not be generated in the factories, since detailed information for test generation is not supplied.

Soldering process should be optimized for each kinds of circuits.

[Requirements] powerful and expensive testers test vectors and/or test generation for locating open leads

Development of vectorless test method for locating open leads

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Test Method Proposed in BTW’07Test based on supply current of our test circuitTest process:

[1]Attach a test probe to the top of a targeted input lead

[2]Provide AC signal

[3]Measure iDDT(t)

[4]If Eq.(1) is satisfied, an open occurs at the targeted input lead.

iDDT(t)≥Ith (1)

(rms)Open at an output lead is detected as open at an input lead.

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Property Used in Our TestIf either Vi=VDD or Vi=0V, IDD=0If Vi1<Vi<Vi2, large supply current flows into a CMOS INV

ICs.

(a)Measurement Circuit

(b)DC characteristicsVi

Vth Vi2Vi1

IDDIDDVo

nMOS:off pMOS:off

Vo

Vi Vo

IDD

VDD

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Principle of Open Lead DetectionWhen an open occurs at an input lead,

vINV(t) will depend on vs(t).

When Vi1<vINV(t)<Vi2, elevated iDDT(t) will flow.

(b)iDDT(t) waveforms(a)Test of open lead

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Tests of Defect-free CircuitsvINV(t) depends on output voltage from IC#i-1 and iDDT(t) ≈0.

If either H or L is outputted to a targeted lead, the lead will be judged as defect-free.

(a)when L is outputted (b)when H is outputted

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Test Circuits for Detecting Opens in BTW’07Purpose: detect more than one lead simultaneously

(a)Test circuit for locating open (b)Test circuit for detecting open

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Necessity of RT

If a CUT is defect-free, elevated iDDT(t) may flow and the CUT may be destroyed when H and L are outputted.

RT’s makethis current small.

[Our new approach]This circuit is used for locating open leads.

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When high-Z is outputted to a targeted lead in a defect-free circuit, the lead will be judged as defective.= Test vector generation and application are indispensable.

Drawback of Our Test Circuit in BTW’07

highZ

(a)when high-Z is outputted (b)when open lead occurs

Elevated iDDT flows.

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Our Purposes

a. Revise test circuit proposed in BTW’07 so that expected test results can be derived even if high-Z is outputted.

b. Develop test circuit design method for locating open leads

(a)Test circuit in BTW’07 (b)Revised test circuit

revised

Pull-up circuits are added

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Our New Test Method Principle:

Tests with high-Z output leads pulled-up

(ex.)Lead c is pulled-up by Sel2=H

Test process:1. Test stage #1:

Purpose: Locate leads of high-Z signal and open leads

2. Test stage #2:Purpose: Locate open leads from leads derived in Test stage#1

Pull-up circuits

ON

HL

L ≈0

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Test Stage#1Purpose: locate open leads and high-Z onesTest procedure:

[1]All of the targeted leads are pulled-up (Sel1,Sel2,Sel3)=(H,H,H)

[2]For each of targeted leads, Pull-up switch of i-th lead is turned off

by Sel#i=L. If iDDT(t)≥Ith, Sel#i=H.

(ex.) Example of tests

Results: (Sel1,Sel2,Sel3)=(L,H,L)

TestSeq.

Sel11 Sel12 Sel13 iDDTlevel

targetedlead

judgement

1 H H H low - -2 L H H low a not opened3 L L H high c opened or High-Z4 L H L low f not opened

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L

LH→L

Test Stage#2Purpose:

Locate open leads by attaching a pull-up circuit to the input leads of targeted ones

Test Procedure:[1]Pull-up circuit is attached to targeted leads

[2]For each of leads of Sel#i=H, pull-up switch of only the i-th lead is turned

off by Sel#i=L. if iDDT(t)≥Ith, it is determined that

open lead occurs at the i-th lead and Sel#i=H.

(ex.) (Sel1,Sel2,Sel3)=(L,H,L)

Even if high-Z signals are outputted, defect-free circuits will be judged as defect- free by attaching the pull-up circuit.

ON

Test Stage#1 Test Stage#2

off

off

off

ZL

H

L

H

H

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L →L →LH→L →H

It can be judged what leads are opened even if high-Z signals are outputted.

Example of Open Lead LocationTest Stage#1 Test Stage#2

off

off

ZL

H

??

H

H

LHH

H→H→LON

ON

(a) test stage#1

(b) test stage#2

on

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Test Circuit Design

Goal: specify RT for defect-free circuits to be judged as defect-free.

pull-up circuit for H output

pull-down circuit for L output

(b)Equivalent circuit

H

L

(a)Test circuit in test stage#1

L

L

(c)Equivalent circuit of (b)# of H output leads =m# of L output leads = n

m-parallel

n-paralleloff

off

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Conditions to be SatisfiedConditions for defect-free

circuits to be judged as defect-free: min(vINVH(t))>Vi2 (2)

max(vINVL(t))<Vi1 (3)

2.01.00

0

5.0

-1.0

time[ms]

2.01.00

0

-3.0

3.0

time[ms]

v S(t

) [

V]

v IN

VH(t

),v I

NV

L(t)

[V

]

vINVH(t)

vINVL(t)

Vi2

Vi1

max(vINVL(t))

min(vINVH(t))

(a)Equivalent circuit (b)Input voltage of INVs in defect-free circuit tests

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Test Circuit DesignTest circuit design for N(=m+n) leads

m: # of H outputted leads n: # of L outputted leads

tpstntptnS

SnontpDDnonSINVH RnRRRRmR

VRRVRmRV

tpstntptnS

SpontnDDTStnTtnSINVL RnRRRRmR

VRRVRnRRRRmRV

)(

ponTtp RRR

nonTtn RRR

2iINVH Vtv ))(min(

1iINVL Vtv ))(max(

Vth Vi2Vi1

IDDIDDVo

nMOS:off pMOS:off

Vo

(a)Measurement Circuit

(b)DC characteristics

Vi Vo

IDD

VDD

where

for m=N-1,n=1

for m=1,n=N-1

worst-case design

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Experimental EvaluationPurpose: Examine feasibility of

our test circuit designCUT: # of leads =50

[Specifications] VDD=5.0, V i1=0.8, V i2=4.2,

Rpon=2.3k, Rnon=3.0k from IC#i-1

Vs=VDD/2=2.5, Rs=100

Derivation of RT

RT≥9.3k from min(v INVH)>V i1, RT≥23.5k from max(vINVL)<V i2

RT=26k

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Evaluation Results

Evaluation by Spice simulation with RT=26k

(a)defect-free circuit (b)circuit having an open lead

Expected test results are obtained with the test circuit designed by our design method.

VSD: Voltage of open lead

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ConclusionA new test circuit for locating open leads of CMOS QFP ICs

[features] Simple test circuit Vectorless test method

Open leads can be located in subcontract soldering factories.

Test circuit design method[Evaluation by SPICE simulation] 50 leads are tested with the test circuit designed by our design method

successfully.

Development of test probesOpen lead location in real ICs with our test circuit

Future worksFuture works