Post on 06-Nov-2020
1Kahng ConFab-2015, 150521
System Integration and System Driver Roadmaps in ITRS 2.0
Andrew B. KahngCSE and ECE Departments, UC San Diego
abk@ucsd.eduhttp://vlsicad.ucsd.edu/
2Kahng ConFab-2015, 150521
Outline• Introduction: System Integration Roadmapping in ITRS2.0• Smartphone Driver: IoT (People)• Microserver Driver: IoT (Cloud)• IoT Driver: IoT (Things)• Summary
[source]http://www.ti.com/ww/en/internet_of_things/pdf/14‐09‐17‐IoTforCap.pdf
3Kahng ConFab-2015, 150521
Design & System Drivers
INTC
PIDSId,sat, Isd,leak
CV/I,fT
FEP
LITHO
Test
#cores, max IO freq
ITRS1.0: IC-Centric Roadmap
ORTCs
• max chip power• layout density• transistor count• chip size• #distinct cores• #cores• max on‐chip freq• product/market
drivers
Fundamental Models
A&P
#IOs, max power, thermal, TSV/3D roadmap
4Kahng ConFab-2015, 150521
Market, Application Contexts
Source: Internet of Things (IoT): A Vision, Architectural Elements, and Future Directions, Future Generation Computer Systems 29 (2013), pp. 1645-1660.
5Kahng ConFab-2015, 150521
ITRS2.0: Applications, Markets, Systems
Source: Dr. P. Gargini, ITRS
6Kahng ConFab-2015, 150521
Outline• Introduction: System Integration Roadmapping in ITRS2.0• Smartphone Driver: IoT (People)• Microserver Driver: IoT (Cloud)• IoT Driver: IoT (Things)• Summary
[source]http://www.ti.com/ww/en/internet_of_things/pdf/14‐09‐17‐IoTforCap.pdf
7Kahng ConFab-2015, 150521
Definition: Smartphone Driver• Smartphone mobile SOC platforms are interfaces to
humans (“people” in IoT infrastructure)• Portable and wireless applications: smart media-
enabled telephones, tablets and digital cameras• Products IN this class: iPhones and iPad• Products NOT IN this class: Snapdragon 810 / Apple A6
(processors instead of platforms), iWatch• Why a System Driver
• Prominence of mobile, communication markets• Strict power budget with uncompromising performance• Drives heterogeneous integration of components and
outside system connectivity
8Kahng ConFab-2015, 150521
Smartphone Driver Evolution• SOC-Consumer Portable (ITRS1.0 Driver) IC product
evolves into ITRS 2.0 Smartphone Driver by adding additional components
Audio Bluetooth Multi‐mode modemVideo Wifi
SOC-CP (ITRS 2013)
SOC-CP
BB/AP PM
Gyrometer
RF Tuner and Demodulator
Antenna Switch
TransceiverReceiver
Bio Sensor
NFC
9Kahng ConFab-2015, 150521
Evolution of Smartphone Metrics• Metrics from SOC-CP (old)
• #AP cores• #GPU cores remains• MPU frequency
• Several new metrics have been added for• Form factor scaling• Display size scaling• Memory size and bandwidth scaling• Data communication bandwidth scaling
10Kahng ConFab-2015, 150521
Summary of Metrics: Smartphone• #AP cores
• Platform complexity and performance • #GPU cores
• Complexity and graphic performance • Max frequency (GHz)
• Performance and power consumption • #MPixels of display
• Graphic performance and system bandwidth • Mem BW (Gb/s)
• Memory performance and system bandwidth • #Sensors
• Peripheral diversity • #Antennas
• Complexity of RF subsystem• #ICs
• System complexity and BOM cost • Cellular data rate (MB/s)
• Design requirement for RF subsystem and modem performance• WiFi data rate (Mb/s)
• Design requirement for WiFi subsystem and modem performance• Board area (cm2)
• System form factor• Board power (mW)
• System power
11Kahng ConFab-2015, 150521
Smartphone Block Diagram Evolution (2002)PA x1
RF Switch x1SAW x3
Transceiver x1VCO x1
TCXO x1
BT BB x1BT Transceiver x1
Analog Interface x1BB Processor x1
Image Processor x1
PMIC x1DC-DC x2
Current Gauge x1 LCD Driver x1
4MB SDRAM x116MB NAND Flash x1
4MB NOR Flash x1
VGA Imaging Sensor x1
Power / Analog
Connections RF Sensor
AP / BB + Multimedia
Memory
Display + Input devices
GSM
[Source: TechInsights]
12Kahng ConFab-2015, 150521
Smartphone Block Diagram Evolution (2013)
PA x4PA controller x1
GPS LNA x1GSM+CDMA+WCDMA+GPS Transceiver x1
Antenna Switch
BT + WiFi + FM BB x1
App Processor x1PMIC x1
Audio Amplifier x1Power IC x8 LCD Driver x1
Touchscreen Controller x1
512MB DDR2 x14GB NAND Flash x1
Memory Controller x1
5M Imaging Sensor x1VGA Imaging Sensor x1
Accelerometer x1Flashlight Driver x1
Proximity Sensor x1
Power / Analog
Connections RF Sensor
AP / BB + Multimedia
Memory
Display + Input devices
Multimode
Notes:1. All multimedia features are on AP2. Audio output circuits integrated into
one IC3. BT, WiFi, and FM (baseband)
integrated into one IC4. Touchscreen introduced5. Memory scaling up
[Source: TechInsights]
13Kahng ConFab-2015, 150521
Low/Mid BandPA/ Antenna
Switch ModuleRxD Switch
High Band PAEnvelope Power TrackerDiversity Antenna Tuner
Power ManagementPlatform
Power Management
LCD DriverTouchscreen Controller
NAND Flash
Environment Sensor Complex
Gestures
Power / Analog
Connections RF Sensor
AP / BB + Multimedia
Memory
Display + Input devices
Multimode Front Imaging SensorBack Imaging Sensor
Positioning Imaging Sensors
App Processor
GPU
LP Core
HP Core
Display engine
Dual ISP
DSP Sensor engine
Multimedia
DRAM controller
locationModem
2x2 WLANBT4.1
NFC
http://www.anandtech.com/show/7925/qualcomms-snapdragon-808810-20nm-highend-64bit-socs-with-lte-category-67-support-in-2015
USB 3.0
Smartphone Block Diagram Evolution (2015)
14Kahng ConFab-2015, 150521
Smartphone Trends Beyond 2015• Market: computer vision, 2D-to-3D reconstruction
• Multiple image sensors (e.g., Kindle Fire has four additional VGA sensors for 3D application)
• Market: data mining of user behavior and HCI applications• Multiple sensors required to monitor environmental events • Aggressive power management with multiple sensors (e.g., Apple A7
use of co-processor as sensor hub)
• Integration: MEMS integration (e.g., six-axes (gyro xaccelerometer) in a package)
• Block Diagram beyond 2015 • Alt-1 (through 2019) has similar organization as smartphones in 2015
but integrates more sensors, sensor hub and antennas• Alt-2 (2020 and beyond) integrates several functions into the AP
• System optimizations drive integrations and dis-integrations at SOC, SIP level [Sources]
http://www.techinsights.com/teardown.com/amazon‐fire‐phone/http://www.invensense.com/mems/gyro/mpu6500.htmlhttp://en.wikipedia.org/wiki/Apple_M7
15Kahng ConFab-2015, 150521
Smartphone Block Diagram Alt-1 (-2019)
PAPA controller
GPS LNAGSM+CDMA+WCDMA+GPS Transceiver
Antenna Switch
BT + WiFi + FM BB
App Processor x1PMIC
Audio AmplifierPower IC
LCD DriverTouchscreen Controller
DDR2NAND Flash
Memory Controller
6 Axis Motion SensorProximity Sensors
ALSTemperature sensor
Power / Analog
Connections RF Sensor
AP / BB + Multimedia
Memory
Display + Input devices
Multimode
[Source]: TechInsightsAmazonApple
13M Imaging Sensor x12.1M Imaging Sensor x1VGA Imaging Sensor x4
Sensor Hub
• Similar organization as smartphones in 2014-2015• Integration of more sensors, antennas, sensor hub
16Kahng ConFab-2015, 150521
Multimode RF for 2G, 3GLTE
mm-WaveBT
WirelessXX (= voLTE, LTE-A, etc.)
PMICAudio Amplifier
Power IC
LCD DriverTouchscreen Controller
NAND Flash
Environment Sensor ComplexXX (= Biometric,
health, etc.)
Power / Analog
Connections RF Sensor
AP / BB + Multimedia
Memory
Display + Input devices
MultimodeFront Imaging SensorBack Imaging Sensor
Positioning Imaging Sensors
LPcores
App Processor (stacked)
SDRBaseband
Core
GPUCore
LPcores
eDRAM
• Multiple functions integrated into AP, e.g., heterogeneous memory, SDR BB
• Integration of more sensors, antennas• SDR = Software-Defined Radio
Smartphone Block Diagram Alt-2 (2020+)
17Kahng ConFab-2015, 150521
Roadmaps for #Cores, Max Freq
• #AP cores: This is the metric to evaluate AP performance and design complexity. More AP cores can also allow higher functionality integration. There will not be more co-processors for new features if AP cores can provide enough performance. (But low power requirement may be exception. For example, Apple M7.)
• #GPU cores: This reflects the graphics processing capacity for 3D, holographic. Heterogeneous computing and programmability increases #GPU cores and other accelerators to be integrated with the GPU cores. Beyond 2019, context-based computing will drive #cores for both AP and GPUs
• Max freq: Linear growth of 4% per year due to power constraints. In 2029, the max power is ~12W, which will drive low-power design methodologies
0.0
2.0
4.0
6.0
8.0
2005 2010 2015 2020 2025 2030 2035
Max freq (GHz)
0
5
10
15
20
2005 2010 2015 2020 2025 2030 2035
#AP cores
#AP cores = 1.0 * 1.14(Year – 2007)
0
100
200
300
400
2005 2010 2015 2020 2025 2030 2035
#GPU cores
#GPU cores = 2.0 * 1.26(Year – 2007)
Max freq = 2.3 * 1.04(Year – 2011)
18Kahng ConFab-2015, 150521
Roadmaps for Sensors, Antennas, #ICs
• Sensors: Diverse sensors such as environment/ambience, accelerometers, health, vibration till 2019.These grow due to proliferation of IoT, context-based computing, pressure, gyro, acoustic, light, etc. However, beyond 2013 the number of sensors saturate due to the form factor limitations of a smartphone.
• Antennas: Diverse antennas for WiF, BT, and cellular. The diversity is driven by WiFi standards (e.g., 802.11ac, ad, etc.) and cellular (e.g., LTE-Advanced, TD-LTE, VoLTE). IoT and context-based computing will push WiFi and cellular standards and their BW requirements. Beyond 2021, the number of antennas saturate but standard evolve and increase the bandwidth.
• #ICs: There is an increase and then decrease due to integration and deintegration of functions (e.g., PEs, sensor hubs, antennas)
0
10
20
30
2000 2010 2020 2030 2040
#Sensors
0
5
10
15
20
2000 2010 2020 2030 2040
#Antennas
0.0
5.0
10.0
15.0
2000 2010 2020 2030 2040
#ICs
#Sensors = 7 + (Year – 2009) * 0.85 #Antennas = 7 + (Year – 2009) * 0.4
#ICs = 10 - (Year – 2009) * 0.15
19Kahng ConFab-2015, 150521
Roadmaps for Display Pixels, Memory BW
• #MPixels: Display pixels driven by high-definition standards (e.g., 720p, 1080p, 4K). #bits per pixel and refresh rates do not scale per year significantly (e.g., #bits per pixel limited to 64bits and refresh rate limited to 120Hz, 240Hz for 3D). Large display sizes drive up memory BW requirements. By 2029, super HD resolutions of 7680 x 4320 will increase memory BW requirements to 144Gb/s [http://en.wikipedia.org/wiki/Ultra_high_definition_television]
• Mem BW: This is defined as the BW between AP and off-chip DRAMs. This reflects the requirement for memory integration technologies. Higher mem BW is due to advanced WiFi, cellular standards, display frame rates and evolution of context-based computing and on-body sensors that’ll require user-specific information to be stored and retrieved when the user’s environment changes. In 2029, the memory BW is 525Gb/s to support super HD display frame rates. The energy consumption till 2019 is ~25pJ/bit and after that around 10pJ/bit with optical interconnects/on-chip plasmonics [https://www.cs.ucsb.edu/~sherwood/pubs/JETCAS-12-plasmon.pdf], which is ~5.3W for 525Gb/s memory BW. This is larger than total smartphone max power (~4W). Therefore, aggressive memory power management techniques will be needed to reduce this power.
0.0
10.0
20.0
30.0
40.0
2005 2010 2015 2020 2025 2030 2035
#MPixels
#MPixels = 0.7 * 1.27(Year – 2013)
0.0100000.0200000.0300000.0400000.0500000.0600000.0
2005 2010 2015 2020 2025 2030 2035
Mem BW (Mb/s)After calibration with 2014 data pointMem BW = 136000 * 1.09(Year – 2014) ; Year > 2014
20Kahng ConFab-2015, 150521
Outline• Introduction: System Integration Roadmapping in ITRS2.0• Smartphone Driver: IoT (People)• Microserver Driver: IoT (Cloud)• IoT Driver: IoT (Things)• Summary
[source]http://www.ti.com/ww/en/internet_of_things/pdf/14‐09‐17‐IoTforCap.pdf
21Kahng ConFab-2015, 150521
Definition: Microserver Driver• Microserver (IoT cloud) platforms are compact
servers with improved power efficiency compared to conventional servers• Products is IN this class: HP Moonshot, HP ProLiant servers• Products NOT IN this class: Intel Atom processor (not a
platform)• Why a System Driver
• Demand for low-latency data processing• Demand to reduce CO2 emission and cooling expenses by
improving datacenter power efficiency• Realization of warehouse computer paradigm
22Kahng ConFab-2015, 150521
Microserver Driver Evolution• MPU-HP (high-performance MPU IC driver) is incorporated into
the microserver (ultimately, server / datacenter) System Driver
SRAM1
core1 core2
core3 core4Uncore
SRAM3
SRAM2
SRAM4
SRAM1
core1 core2
core3 core4Uncore
SRAM3
SRAM2
SRAM4
SRAM1
core1 core2
core3 core4Uncore
SRAM3
SRAM2
SRAM4
SRAM1
core1 core2
core3 core4Uncore
SRAM3
SRAM2
SRAM4
4 MPU-HP (ITRS 2013)HP ProLiant Microserver with
16 cores
• Metrics evolved from MPU-HP in ITRS 1.0• MPU frequency, logic/SRAM breakdown, #cores, …
• New metrics added to account for network / backplane bandwidth, storage capacity, …
23Kahng ConFab-2015, 150521
Summary of Metrics: Microserver• #MPU cores/rack unit
• Density of cartridges• Max Frequency (GHz)
• Performance• DRAM capacity (GB)/ rack unit
• Local memory capacity• DRAM BW (GB/s)
• Intra-node system bandwidth• Off-MPU BW (GB/s)
• Inter-node system bandwidth• MPU frequency × #Cores (GHz)/rack unit
• Per-node performance
24Kahng ConFab-2015, 150521
Microserver Block Diagram (2012)
DDR3
MPU‐0
Memory Controller
PCIe 2.0× 8
Cores
GbE × 2Local SATA Drives
Peripherals
10.7GB/s
1GB/s
2GB/s
[source]http://h20195.www2.hp.com/v2/GetDocument.aspx?docname=4AA5‐0893ENW&doctype=data%20sheet&doclang=EN_US&searchquery=&cc=us&lc=enhttp://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom‐processor‐s1200‐datasheet‐vol‐1.pdfhttp://en.wikipedia.org/wiki/List_of_device_bit_rates
1GB/s
25Kahng ConFab-2015, 150521
Microserver Block Diagram (2012)
DDR3
MPU‐0
Memory Controller
PCIe 2.0× 8
Cores
GbE × 2Local SATA Drives
Peripherals
10.7GB/s
1GB/s
2GB/s
[source]http://h20195.www2.hp.com/v2/GetDocument.aspx?docname=4AA5‐0893ENW&doctype=data%20sheet&doclang=EN_US&searchquery=&cc=us&lc=enhttp://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom‐processor‐s1200‐datasheet‐vol‐1.pdfhttp://en.wikipedia.org/wiki/List_of_device_bit_rates
1GB/s
Microserver revolution – since 2012Compared to conventional server: 1. Few ( 4) MPU per server cartridge2. Significant reduction of MPU performance (2.0GHz) and system-level bandwidth
(PCIe × 8)3. PCIe hub is integrated into MPU4. No auxiliary chipset
-- DRAM and peripherals are connected to MPU-- BOM cost and integration effort are reduced
5. Inexpensive components-- SAS SATA-- Buffered DDR3 Unbuffered DDR3
26Kahng ConFab-2015, 150521
Microserver Block Diagram (2015)
DRAM
MPU‐0
Memory Controller
Electrical Interconnects (PCIe 3.x)
Cores
Optical Interface
Local Drives
Peripherals
Cores Cores
Low power cores
Low power cores
Low power cores
Accelerator AcceleratoreDRAM
Optical Networks
• Introduction of optical interconnects, mainstream heterogeneous cores
“22-nm Next-Generation IBM System z Microprocessor”, ISSCC 2015 (proof point for eDRAM and memory controller integration in cores)
27Kahng ConFab-2015, 150521
Microserver Trends Beyond 2015
• Computational power density challenges may imply SOC/ASIC-like trajectories
• More light cores• More peripherals• More application-specific accelerators• More complicated inter-IP communication fabrics
• Higher integrated network bandwidth to address system throughput requirements under strict form-factor and power constraints
• Block Diagram beyond 2015 • Alt-1 (through 2019) has similar organization as microservers in
2014/2015 with architectural improvements in MPUs and peripherals• Alt-2 (2020 and beyond) integrates optical interconnects and
heterogeneous cores
28Kahng ConFab-2015, 150521
Microserver Block Diagram Alt-1 (-2019)
DDRXX
MPU‐0
Memory Controller
PCIe XX Hubs
Cores
Local SATA (or XX) Drives
Peripherals
Cores Cores
Cores Cores Cores
Accelerator Accelerator
• Similar organization as microservers in 2014/2015
• Architectural improvements in components, e.g., PCIe, DRAM, cores, etc.
• Timeline is beyond 2015, but up to 2019
Optical Interface
Optical Networks
29Kahng ConFab-2015, 150521
Microserver Block Diagram Alt-2 (2020+)
DRAM + Optical storage
MPU‐0
Memory Controller
Hub for optical Electrical
Interconnects
Cores
Fiber Interface
Local Drives
Peripherals
Cores Cores
Low power cores
Low power cores
Low power cores
Accelerator AcceleratoreDRAM
Optical Networks
• Introduction of on-chip optical interconnects, mainstream heterogeneous cores
• Timeline is from 2020 and beyond
30Kahng ConFab-2015, 150521
Roadmaps for #Cores, Max Frequency
• These metrics are driven by the max power delivery to a rack. Most of the jobs on microservers are batch-processed, which drives the number of low-power cores grow in the roadmap. The growth is constrained by power and cost.
• The frequency roadmap is same as the existing MPU-CP roadmap and driven by real-time jobs (e.g., video streaming, maps, virtualization) [http://forums.whirlpool.net.au/archive/2234398]. The roadmap is limited by power, which grows to ~90W in 2029 and will drive low-power design methodologies.
0
200
400
600
800
1000
1200
2009 2011 2013 2015 2017 2019 2021 2023 2025 2027 2029
MPU frequency x #Core (GHz) / rack unit
#MPU cores/rack unit = 55 * 1.24(Year – 2013) ; Year ≤ 2019= 45 * 1.16(Year – 2019) ; Year > 2019
0
20
40
60
80
100
120
140
160
180
2009 2011 2013 2015 2017 2019 2021 2023 2025 2027 2029
#MPU cores / rack unit
#MPU cores/rack unit = 16 * 1.19(Year – 2013) ; Year ≤ 2019= 45 * 1.12(Year – 2019) ; Year > 2019
0
1
2
3
4
5
6
7
2009 2011 2013 2015 2017 2019 2021 2023 2025 2027 2029
Max frequency (GHz)
Max freq = 3.46 * 1.04(Year – 2013)
Follows MPU-HP/CP trajectory
Performance challenge, might need better processor / memory architecture
31Kahng ConFab-2015, 150521
Roadmaps for DRAM capacity, BW, Off-MPU BW
• DRAM cap per rack unit is driven by the number of cores in a rack and redundancy due to using advanced RAID [http://www.newegg.com/Product/Product.aspx?Item=N82E16859107052] and cloud data storage needs
• IBM expects 2TB / 1U in 2019 [https://www.power.org/wp-content/uploads/2012/10/15.-IBM-DB2_lui-v5.pdf]• DRAM BW is driven by faster clocks, the number of cores and smaller latency requirements for high-priority tasks (e.g., ads, maps)
[http://www.theregister.co.uk/2013/09/04/intel_avoton_rangeley_atom_c2000]• Off-MPU BW is driven by both batch and real-time applications (e.g., queries, video streaming)
0
500
1000
1500
2000
2500
3000
2009 2011 2013 2015 2017 2019 2021 2023 2025 2027 2029
DRAM BW (GB/s)
DRAM BW= 51.2 * 1.26(Year – 2013)
1
10
100
1000
10000
100000
1000000
2010 2015 2020 2025 2030
DRAM capacity / rack unit (GB)
DRAM / Rack Unit (GB)= 128 * 1.58(Year – 2013)
0100200300400500600700800900
2009 2014 2019 2024 2029 2034
Off‐MPU BW (GB/s)
Off-MPU BW= 32 * 1.28(Year – 2013) ; Year ≤ 2019= 144 * 1.18(Year – 2019) ; Year > 2019
Grows as #cores increase per rack
32Kahng ConFab-2015, 150521
Outline• Introduction: System Integration Roadmapping in ITRS2.0• Smartphone Driver: IoT (People)• Microserver Driver: IoT (Cloud)• IoT Driver: IoT (Things)• Summary
[source]http://www.ti.com/ww/en/internet_of_things/pdf/14‐09‐17‐IoTforCap.pdf
33Kahng ConFab-2015, 150521
Definition: IoT (Things) Driver• IoT (Things) are extremely compact, low-power MCU
platforms with sensors which can be ubiquitously deployed in the environment• Product (research) IN this class: Smart Dust; Nest• Products NOT IN this class: MEMS chip, MCU, proximity sensors
• Why a System Driver• Drives display market (huge number of devices to be deployed)• Drives robust reliability and battery requirements to work under
harsh environmental conditions • Drives extremely low suspend power requirement• Increasing performance requirement• Drives heterogeneous integration and connectivity requirements
(packaging, interconnect, panel technologies)
34Kahng ConFab-2015, 150521
IoT Driver Introduction• IoT is a new driver (not in ITRS 1.0) for context-aware
computing, harmonizing the way humans and machines connect using common public services
[Source]http://www.ti.com/ww/en/internet_of_things/pdf/14‐09‐17‐IoTforCap.pdf
35Kahng ConFab-2015, 150521
Summary of Metrics: IoT (Things)• Power sufficient lifetime without battery replacement
• Lowest system supply voltage (V)• Battery capacity (mA‐h)• Deep suspend current (nA)• DC‐DC efficiency (%)• DC‐DC power density (W/mm^2)• Peak Tx/Rx current (mA)
• Performance sufficient computation capacity for applications• MCU #Cores• MCU #FPUs• MCU IDD / Operation frequency (uA/MHz)• Max MCU Frequency (MHz)• MCU SRAM Size (KB)• MCU Flash Size (KB)• MCU MIPS
• Form factor small system size to simplify deployment• MCU Package size (mm^2)
• Peripheral sufficient interfaces to interact with physical world • #Integrated Comm. Protocols of MCU• # of MCU GPIOs• #ADC channels• ADC resolutions• #PWM
• Reliability robustness under harsh environment• Lifetime #access of NVM memory• Device lifetime (years)• Max system supply voltage (V)
36Kahng ConFab-2015, 150521
ITRS Challenges From IoT• Potential new device, interconnect roadmaps
• Very low duty cycle to reduce the lifetime energy consumption• Fine-grained power modes to adapt to application contexts
• Potential new integration technologies• Complex communication protocols, large bandwidth requirements• Heterogeneous integration in stacked ICs
(WAS) (IS)
http://cache.freescale.com/files/microcontrollers/doc/brochure/BRLWPWR.pdf
37Kahng ConFab-2015, 150521
IoT Integration Challenges• IoT SOCs require on-chip NVM for storing programs and data new NVM technology to dominate[1]
• Fin discreteness integrated RF, analog circuits may favor FD-SOI over FinFET, unlike pure logic devices[2]
[1] http://www.cypress.com/?docID=45736[2] http://www.eetimes.com/document.asp?doc_id=1325866&
STM technology roadmap for IoT SOC[2]Comparison of process integration between floating gate and SONOS[1]
38Kahng ConFab-2015, 150521
Supply Voltage, Suspend Current
00.20.40.60.81
1.21.41.61.8
2010 2015 2020 2025 2030
Lowest system supply voltage (energy source) (V)
0
20
40
60
80
100
120
2014 2016 2018 2020 2022 2024 2026 2028 2030
Deep suspend current (nA)
• Assumption: energy harvesting introduced in 2017• Lowest supply voltages drops significantly• Deep suspend current reaches ~10nA level concurrent with deployment of
energy harvesting
[source] http://eh‐network.org/files/human_power.pdfhttp://www.cymbet.com/pdfs/Powering‐Wearable‐Technology‐and‐the‐Internet‐of‐Everything‐WP‐72‐10.1.pdf
39Kahng ConFab-2015, 150521
DC-DC Efficiency, Power Density• Data from published articles, product datasheets• Driven by low-power requirement
0.00
0.20
0.40
0.60
0.80
1.00
1.20
2014 2016 2018 2020 2022 2024 2026 2028 2030
DC‐DC efficiency (%)
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
2014 2016 2018 2020 2022 2024 2026 2028 2030
DC‐DC power density (W/mm^2)
40Kahng ConFab-2015, 150521
Peak Tx/Rx Current, Power
0.00
10.00
20.00
30.00
40.00
50.00
60.00
2014 2016 2018 2020 2022 2024 2026 2028 2030
Peak Tx/Rx current (mA)
• Power consumed by connectivity is critical to IoT• High peak currents inconsistent with small battery size, energy harvesting• Improved system-level power efficiencies expected (e.g., “do nothing well”)
Power overhead (normalized to BW) = (energy per bit in uJ) / (bit/sec) = uW/bit
0.00
0.50
1.00
1.50
2.00
2.50
3.00
2014 2016 2018 2020 2022 2024 2026 2028 2030
Tx/Rx power per bit (uW/bit)
41Kahng ConFab-2015, 150521
Module Footprint• System form factor is limited (e.g., by battery technology) in near term• After 2017, form factor scales as devices go to 3D / 2.5D or better analog-
digital system partitioning, integration• Scaling of passives (number, size) eventually blocks form factor scaling novel solutions needed
0.00
5.00
10.00
15.00
20.00
25.00
30.00
35.00
40.00
45.00
2014 2016 2018 2020 2022 2024 2026 2028 2030
Module footprint (mm^2)
42Kahng ConFab-2015, 150521
Outline• Introduction: System Integration Roadmapping in ITRS2.0• Smartphone Driver: IoT (People)• Microserver Driver: IoT (Cloud)• IoT Driver: IoT (Things)• Summary
[source]http://www.ti.com/ww/en/internet_of_things/pdf/14‐09‐17‐IoTforCap.pdf
43Kahng ConFab-2015, 150521
Bigger Picture • IoT (Things) still a developing product category
• New applications, drivers and integration challenges are expected• Not-yet-roadmapped applications
• Automobile electronics (ADAS, transportation management, self-driving car)
• Smart electronics (wearables, etc.) + implied big data applications
[Source] R. Aschenbrenner, “Hetero‐integration for cyber physical systems at wafer‐level and panel‐level”, INC‐11, 2015.
44Kahng ConFab-2015, 150521
Technology Requirements From Applications• Example: Roadmap for computer vision support• Middle 200X RFID tags/facilitating routing = barcode scanning • Early 201X gesture detection• Early 201X transport = license plate detection• Middle 201X locating people = face recognition• Late 201X ubiquitous positioning = (highly sensitive) security/surveillance• Early 202X physical-world web = realtime, high resolution machine vision
[source] http://en.wikipedia.org/wiki/Internet_of_Things#/media/File:Internet_of_Things.png
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Conclusion• ITRS 2.0 System Integration Focus Team: roadmaps of
system drivers that drive semiconductor and design technologies• Initial proofs of concept (2014): Smartphone, Microserver• 2015 target: “IoT (Things)”
• Roadmapping process based on calibration data (product teardowns and physical analyses, product datasheets), block diagram evolution, extrapolation
• Key interactions in ITRS 2.0 with Heterogeneous Integrationand Outside System Connectivity
• Your feedback and inputs, contributions welcome!My email: abk@ucsd.edu
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Acknowledgments• Dr. Juan-Antonio Carballo, Dr. Paolo Gargini• ITRS 2.0 System Integration Focus Team, and FT leads• Wei-Ting Jonas Chan, Siddhartha Nath and other UCSD
VLSI CAD Laboratory members • Recent publications:
• J.-A. Carballo, W.-T. J. Chan, P. A. Gargini, A. B. Kahng and S. Nath, "ITRS 2.0: Toward a Re-Framing of the Semiconductor Technology Roadmap", Proc. ICCD, 2014, pp. 139-146.
• W.-T. J. Chan, A. B. Kahng, S. Nath and I. Yamamoto, "The ITRS MPU and SOC System Drivers: Calibration and Implications for Design-Based Equivalent Scaling in the Roadmap", Proc. ICCD, 2014, pp. 153-160.
• “ITRS 2.0: Top-Down System Integration” http://semimd.com/blog/2015/04/22/itrs-2-0-top-down-system-integration/
• A. B. Kahng, "The Road Ahead: Predicting the future of information technology and society", IEEE Design and Test, Nov-Dec 2012, pp. 101-102.
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Thank You !
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BACKUP
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Computer Vision Power / Performance Reqts• Performance: required Mpixel/sec for CV applications• Power efficiency: nJ/pixel (characterized from FPGA + mobile SOC CV [1]) • At < 0.1W, severe power challenges for CV applications on IoT/wearable
devices technology and system architecture solutions needed
Year 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029Resolution QVGA VGA VGA HD720 HD1080 VGA
FPS 5 15 30 30 30 240Required Mpixel/sec
(data point) 0.4 5 9 28 62 73Required Mpixel/sec
(est.) 0 1 5 6 8 10 13 16 20 25 31 40 50 63 79 99 125 158 198 249 314 395Energy per pixel (nJ) 231 231 231 231 231 231 231 231 231 231 231 231 231 231 231 231
Power (W) 3 4 5 6 7 9 12 14 18 23 29 36 46 58 72 91
0
100
200
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2005 2010 2015 2020 2025 2030 2035
Required Mpixel/sec (data point) Required Mpixel/sec (est.)
1
10
100
2005 2010 2015 2020 2025 2030 2035
Power (W)
Power constraint ~0.1W(from ARM roadmap)
[1] http://www.inf.ethz.ch/personal/pomarc/pubs/HoneggerIROS14.pdf