Post on 15-Feb-2018
www.sciencemag.org/content/355/6322/271/suppl/DC1
Supplementary Materials for
Scaling carbon nanotube complementary transistors to 5-nm gate lengths
Chenguang Qiu, Zhiyong Zhang,* Mengmeng Xiao, Yingjun Yang, Donglai Zhong,
Lian-Mao Peng*
*Corresponding author. Email: zyzhang@pku.edu.cn (Z.Z.); lmpeng@pku.edu.cn (L.-M.P.)
Published 20 January 2017, Science 355, 271 (2017)
DOI: 10.1126/science.aaj1628
This PDF file includes:
Materials and Methods
Fig. S1 to S15
References
1
Supplementary Materials for
Scaling carbon nanotube complementary transistors to 5-nm gate
lengths
Chenguang Qiu, Zhiyong Zhang*, Mengmeng Xiao, Yingjun Yang, Donglai Zhong
and Lian-Mao Peng*
Key Laboratory for the Physics and Chemistry of Nanodevices and Department of
Electronics, Peking University, Beijing 100871, China
*Correspondence to:
E-mail: (Z.Y.Z.) zyzhang@pku.edu.cn; (L.M.P.) lmpeng@pku.edu.cn.
This PDF file includes:
Materials and Methods
Figs. S1 to S15
References
Materials and Methods
1. CNT growth and selection
SWCNTs used in this work were directional CNTs array synthesized by two kinds
of CVD methods. One kind of CNTs was directionally grown on a Si substrate
covered with 300 nm SiO2 layer (44), and the other was grown on quartz substrate (45)
followed by a process transferring CNTs arrays to Si/SiO2 substrate. Semiconducting
single-walled CNTs were identified via field-effect measurements using the Si
substrate as the back gate, and then were used for further device fabrication.
2. Fabrication of CNT CMOS FETs
The carbon nanotube CMOS FETs with 10 nm gate length were fabricated using a
top gate structure by a doping-free process similar to previous work (14), except for
the following differences. A double electron - beam - lithography (EBL) / electron -
beam - evaporation (EBE) / lift-off were adopted to form the source and drain
2
contacts respectively to achieve 10 nm channel (19,43). 10 nm Pd film was used as
contacts for p-type FETs and 3/15 nm Al/Sc film was used as contacts for n-type
FETs. The Al film covered on Sc film was used to improve stability of Sc contact in
air. Ultra-thin (with thickness of 3.5 nm) HfO2 film was grown as gate dielectric via
low-temperature ALD of 90℃ with a dielectric constant of 13 (obtained by C-V
measurement), and 15 nm-thick Pd film was deposited as gate electrodes through
EBE. (For the CNT CMOS FETs with gate length larger than 30 nm, 5 nm HfO2 was
used as gate dielectric.) The detailed fabrication process of CNT CMOS FETs is
shown in Fig. S1, device characteristics are shown in Figs. S2-S3.
3. Fabrication of scaled contact length CNT CMOS FETs and small pitch size
inverter
The CNT FETs with scaled contact length Lc were fabricated through a gate-stack-
first process as shown in Fig. S11. At first Al strips with thickness of 30 nm and width
of 35 nm were formed on CNTs through EBL, EBE and lift-off, and were then
oxidized in air at 180℃ for one hour to form Al2O3 around the surface of Al stripe.
Oxygen molecules can diffuse into the interface of Al and CNT to form a layer of
Al2O3 as the gate dielectrics (46), and then the Al2O3/Al gate stack was thus formed
on CNTs. The Al2O3 layer at the sidewalls of gate stack isolates electrically gate
electrode from the source and drain. Then Pd contacts with thickness of 20 nm were
formed for p-FETs through EBL, EBE and lift-off, and 20 nm/3 nm Sc/Al stacked
contacts were formed for n-FETs. The scaled n-FETs were measured in vacuum
(Lakeshore TTP 5 probe station) to prevent Sc contacts (with width of several tens of
nm) from being oxidized from sides especially owing to current induced Joule heat
during electrical measurements.
4. Fabrication of graphene-contact CNT FETs
We developed a new process to open sub-10 nm gap on graphene by combining
Inductively Coupled Plasma (ICP) etching and electrical burn-down of graphene, and
the detailed process is shown in Figs. S6 and S7. At first we used EBL-patterned Al
film with thickness of 10 nm as the mask to etching graphene by ICP. EBL processes
were adopted respectively to define Al stripes for defining the source regions and for
drain regions, and gaps ranging from 5 nm to 15 nm between Al stripes for the source
3
and for drain were fabricated. After etching graphene through Al-gap by using O2 ICP
process (50 W, 8 seconds), the small gaps on Al were transferred to graphene. Then
the 10 nm Al stripes on graphene were selectively etched using 2% TMAH within 2
min at room temperature. The patterned graphene stripes will possess rough edges
with several burrs, which were originated from the coarse edges of the Al masks.
These burrs may induce conductive filaments across the gap especially in small gap
between the graphene source and drain, and needed to be eliminated. An electrical
burn-down process was used to break the possible filaments, and make sure insulation
between the graphene source and drain. After CVD-derived parallel CNT arrays were
transferred to across the graphene stripes, 4 nm Y2O3 was formed as gate dielectric by
EBE-grown Y film followed by oxidization at 240 ℃ in air for 30 min (47). The G-
contacted CNT FETs were finished after a 30 nm Pd film was deposited by EBE as
top gate electrode and a lift off process.
5. Method to obtain intrinsic gate delay and energy delay product
The intrinsic gate delay is defined as
, (1)
where Vdd is the supply voltage, Ion is the on-state current as defined as the current at
Vgs-Vt=2Vdd/3 (36), and C is the intrinsic gate capacitance defined by
(2)
in which CQ is the quantum capacitance and Cox is the gate oxide capacitance which is
evaluated using
, (3)
where t is the thickness of the gate insulator, r is the radius of the CNT, and and
are the permittivity of vacuum and relative dielectric constant of the dielectric film
respectively.
The energy and delay product is defined as
. (4)
6. Method to estimate the electron number in the channel of a CNT FET
The number of carriers in the channel of a CNT FET is estimated using
. (5)
4
For the FET based on a CNT with a diameter of 1.3 nm, the gate capacitance C is
calculated to be 1.63 pF/cm, we thus obtain
N=Lg / 3.7 nm. (6)
Therefore the number of carriers in the channel is 2.7 for CNT FETs with Lg=10nm,
and is 1.35 for CNT FETs with Lg =5 nm.
7. Growing HfO2 on CNT and graphene
ALD precursors usually do not absorb on the nanotube surface. Here we used an
unconventional way to grow the top gate dielectric. We found that an ultra-thin
amorphous carbon film (thinner than 1 nm here) may be deposited on top of the CNT
during SEM imaging and electron beam lithography process of fabricating small CNT
device, which provides the required nucleation sites for ALD growth of uniform
ultrathin HfO2. To verify this growth mechanism, we show results of ALD grown
HfO2 film in two regions (A and B) in Fig. S12. Region A represents the usual
graphene, region B was scanned by SEM before ALD. It is well known that electron
beam irradiation in SEM will induce carbon contamination, and Fig. S12 clearly
shows that this helps the growth of uniform HfO2 film on graphene.
8. Imaging contacts and SWCNT using different voltages
Imaging CNTs using SEM in top-gated CNT FETs is not easy. In this work, we
developed a method to determine the position of the CNT in the device by using two
images taken with different beam voltages, i.e. imaging CNT using electron beam of 2
kV, and then imaging contacts using electron beam of 30 kV (Fig. S15). To
emphasize the gate length defined by the contacts, we used the SEM image taken at
30 kV electron beam. The position of the CNT is determined by another SEM image
taken at 2 kV electron beam, and the position of the CNT is marked by the dotted line
with the help of the image taken at 2 kV.
5
B
A
Figure S1| Structure and process-flow of 10 nm CNT CMOS FETs. (A) Schematic, Top-view SEM
image, and Cross-sectional TEM image of CNT CMOS FETs. (B) Fabrication process flow of CNT
CMOS FETs. (1). Source regions of P-FETs were patterned by EBL, followed by deposition of 10 nm-
thickness Pd film and then a standard lift-off process. (2). Drain regions of P-FETs were fabricated by
the similar way as the source, and then gaps about 10~20 nm were formed between the source
electrode and drain electrode. (3). Gate regions were patterned by EBL, and then HfO2/Pd gate stack
was grown and formed. The thickness of HfO2 and gate metal is 3.5 nm and 15nm respectively. (4).
Source regions of N-FETs were patterned by EBL, followed by deposition of 15/3 nm Sc/Al film and
then a standard lift-off process. (5). Drain regions of N-FETs were fabricated by the similar way as the
source. Al film with 3nm-thickness was grown to cover Sc film as a protection layer. (6). HfO2/Pd gate
stack was formed.
6
A B
Figure S2| Properties of 10nm CNT CMOS FETs. (A) Gate voltage dependent linear output
conductance and transconductance of 10 nm CMOS FETs. (B) Transconductance comparison between
10 nm CNT CMOS FETs and Si CMOS transistors (Intel’s 14 nm technology). Si CMOS FETs were
driven at bias of 0.7 V for 14 nm node (22), but CNT FETs were driven at ultra-low bias of 0.4 V
(normalized by 125 CNTs/μm). (C) Output characteristics of the 10 nm CNT CMOS FETs. (D)
Transfer characteristics of multiple CNT CMOS FETs at Vds =±0.1 V, including 6 n-FETs and 5 p-
FETs with gate lengths ranged from 10 nm to 20 nm.
-0.4 -0.2 0.0 0.2 0.40
5
10
15
20
11.5 k
I ds(
A)
Vds
(V)
10.5 k
C D
-1.0 -0.5 0.0 0.5 1.01E-12
1E-11
1E-10
1E-9
1E-8
1E-7
1E-6
1E-5
I ds(A
)
Vgs
-Vt(V)
-0.4 -0.2 0.00
2
4
0.0 0.2 0.40
2
4
6
Vds
=0.4VVds
=-0.4V
Vds
=-0.7V
Gm(m
S/
m)
CNT CNT
Intel 14nmGm(m
S/
m)
Vgs
-VT(V)
Intel 14nm
Vds
=-0.7V
Vgs
-VT(V)
0.0
0.2
0.4
0.6
0.0
0.2
0.4
0.6
-1.0 -0.5 0.0 0.5 1.00
20
40
0
20
40
Glin
ea
r(4e
2/h
)
Vds
=0.1VVds
=-0.1V
Vds
=-0.4V
Gm(
s)
Vgs
(V)
Vds
=0.4V
7
Figure S3| Structure and properties of 5nm CNT FETs. (A) Top-view SEM image of a typical 5
nm gate length CNT P-FET. (B-C) Transfer characteristics and linear conductance of four CNT FETs
with gate length ~ 5nm. All curves were measured at Vds= -0.1V, and the best FET presents a high
conductance up to 0.64 G0. (D) Transfer characteristics (Ids~Vgs) of a typical CNT FET with 5 nm Lg
at the bias of Vds= -0.4V and -0.1V. (E) Output characteristics of the same FET as in (D), where |Vgs-
Vt| varies from -0.2 V to 0.8 V with a step of 0.2 V. (F) Vgs dependent transconductance of the same
FET as in (D), at Vds = -0.4 V.
C B
A
-0.4 -0.3 -0.2 -0.1 0.00
5
10
15
20
I ds(
A)
Vds
(V)
Ron
=10k
D E
F
-1.0 -0.5 0.0 0.5
1E-9
1E-8
1E-7
1E-6
1E-5
SS=103 mV/Dec
I ds(A
)
Vgs
-Vt(V)
Lg~5 nm
-1.0 -0.5 0.00.0
0.1
0.2
0.3
0.4
0.5
0.6
Go
n (
G0)
Vgs
-Vt (V)
# 1
# 2
# 3
# 4
-1.0 -0.5 0.0
1E-9
1E-8
1E-7
1E-6
1E-5
I ds (
A)
Vgs
(V)
Vds
= -0.1V
Vds
= -0.4V
-1.0 -0.5 0.00
5
10
15
20
25
30
Gm (S
)
Vgs
(V)
8
Figure S4| Simulations to illustrate electrostatic improvement for a nano-FET. (A-B) By
decreasing the thickness of the source/drain from 10 nm to 3 nm, the SS of a nano FET (Lg=5 nm)
was improved from 96 mV/Dec to 76 mV/Dec. Here, 3 nm HfO2 film was used as gate insulators
and spacers. (C) The transfer curves for two FETs. Simulations are carried out by Silvaco
(http://www.silvaco.com) using a SOI structure with silicon as the channel material
(thickness=1nm). The energy band (Eg) and mobility (μ) of the material is modified to 0.8 eV and
5000 cm2/vs respectively to simulate carbon nanotube property more accurately.
B
C
0.0 0.5 1.0 1.51E-12
1E-11
1E-10
1E-9
1E-8
1E-7
1E-6
1E-5
I ds (
A)
Vgs
(V)
TG, Lg=5nm,
Lch
=11nm, Tsd
=10nm,
TG, Lg=5nm,
Lch
=11nm, Tsd
=3nm
A
9
-1.0 -0.5 0.0 0.51E-12
1E-11
1E-10
1E-9
1E-8
1E-7
1E-6
SS
min =
73 m
V/D
ec
Lg~ 5 nmI ds(A
)
Vgs
-Vt (V)
Figure S5| Graphene-contacted CNT FETs. (A) Schematic diagram of a graphene-contacted (GC)
CNT FET. (B) A top-view SEM image for a typical top-gate CG CNT FET. The scale bar is 200
nm. (C) Transfer characteristics of 7 GCCNT FETs with Lg = 10 nm, presenting an average SS of 66
mV/Dec, at Vds= -0.1 V. (D) Transfer characteristics of 5 GC CNT FETs with Lg ~ 5 nm,
showing a minimum SS of 73 mV/Dec, at Vds= -0.1 V.
Ⅰ
A B
C D
-1.0 -0.5 0.0 0.51E-12
1E-11
1E-10
1E-9
1E-8
1E-7
1E-6
I ds (
A)
Vgs
-Vt(V)
Lg = 10 nm
10
Figure S6| Process flow of GC CNT FETs. (1). CVD-derived graphene film was transferred from
copper foil to the surface of silicon substrate covered by 300 nm SiO2. (2). Source mask arrays were
patterned by EBL, followed by deposition of 10 nm-thickness Al film and then a standard lift-off
process. (3). Drain mask arrays were fabricated by the similar way of source mask arrays, and then
gaps about 5~15 nm were formed between the source Al-masks and drain Al-masks. (4). The 5 nm
gaps on graphene were formed by oxygen ICP with Al masks. Then all of the Al-masks were etched
off by 2% TMAH for 2 min. It’s worth noting that the ICP and Al-etching processes don’t widen the
gap. It is clear to see the 12 nm gap on Al-mask was transferred to graphene without deformation.
Therefore we can deduce size of gap on graphene by measuring the size of gap on Al-masks. (5).
Ti/Au with thickness of 5/30 nm were fabricated as connecting wires and pads, and then the electrical
burn-down process was implemented to eliminate the local conducting filaments across the gaps of
graphene. (6). Transferring CVD-derived CNTs array from quartz to the graphene source and drain
arrays, and etching off the redundant CNTs and graphene by ICP. Single CNTs across the 5nm gap
of graphene were left for the further devices fabrication. (7). Yttrium film was deposited by e-beam
evaporation and then was oxidized at 240 ℃ in air for 30 min to form 4 nm Y2O3. The GC-CNT
FETs were finished after fabrication of gate stack by another EBL, EBE (30 nm Pd film) and a lift-
off process.
11
Figure S7| Detailed process of electrical burning-down between the source graphene and drain
graphene. (A) SEM image of Al-masks shows that the filaments exist between the source and drain
masks after etching. The filaments would cause the conducting channel in the graphene gap after ICP
and clearing up Al masks. The scale bar is 200 nm. (B) Detailed process of electrical burning-down
graphene filaments were divided into two stages. The first stage is to burn down all the conductive
filaments in the gap. However there are still some burrs left at the edges of source and drain, which
will induce field emission at high electrical field. (C) In the second stage, burning cycles were
repeated to trim the carbon atoms in the gap until the field emission current was reduced to 0.1 pA at
bias of 0.5 V. (D) Schematic flow of burning-down process.
0.0 0.5 1.0 1.5
5
10
15
20
25Stage 1:
Filaments #1 and #2
to be burn down
I lea
kag
e(
A)
Vbias
(V)
A
B
C
D
0.0 0.5 1.0 1.5 2.0
1E-13
1E-11
1E-9
1E-7
1E-5
Finished
I lea
kag
e(A
)
Vbias
(V)
Stage 2:
Field emission
to trim the edge of gap
Check
12
Figure S8| Benchmarking CNT CMOS FETs with published Si CMOS transistors. (A) Scaling
of gate delay of CNT CMOS FETs, compared with that of Si CMOS FETs (36, 39), and gate length
ranging from 5 nm to 1um. All data for CNT CMOS FETs are evaluated with Vdd=0.4 V. (B) Scaling
of energy-delay product of CNT CMOS FETs, compared with that of Si CMOS-FETs (36). Squares
represent the data of Si NMOS from ITRS 2013 (39), and the yellow solid squares represent the
solution are known, and the yellow hollow squares represent the solution in industry are unknown.
A B
10 100
1E-30
1E-29
1E-28
1E-27
1E-26
1E-25
ED
P (
Js/
m)
Lg (nm)
2028
10 100
0.1
1
10
Dela
y (
ps)
Lg (nm)
2028
13
Figure S9| CNT CMOS FETs with scaled contacts (A) Schematic diagrams illustrating a small
pitch Al-gate CNT FET using a gate-first process as used in Ref. 13 and 46 of the main text. The
cross section illuminates the Al2O3 gate dielectrics can be formed between CNT and Al gate
electrode. (B)Top-view SEM images of CNT n-FETs with contact length ranging from 100 nm to 25
nm, the channel and gate length are fixed at 50 nm and 30 nm in all devices.
A
B
14
A B
-1.0 -0.5 0.0 0.5 1.0
1E-10
1E-9
1E-8
1E-7
1E-6
1E-5
Vds=0.1V
Vds=0.4V
Vds=-0.1V
SS
=78 m
V/D
EC
Vds=-0.4V
SS
=92 m
V/D
EC
Vgs(V)
|Ids|(A)
-0.4 -0.2 0.0 0.2 0.40
1
2
3
4
5
I ds(A)
Vds(V)
E
-1.5 -1.0 -0.5 0.0 0.5 1.00
2
4
6
8
10
I ds(
A)
Vgs
(V)
25nm
30nm
40nm
55nm
60nm
80nm
-1.5 -1.0 -0.5 0.0 0.5 1.00
2
4
I ds(
)
Vgs
(V)
25nm
50nm
80nm
100nm
-1.0 -0.5 0.0 0.5 1.0 1.50
2
4
6
8
I ds(
)
Vgs
(V)
25nm
30nm
40nm
45nm
50nm
60nm
80nm
100nm
-1.0 -0.5 0.0 0.5 1.0 1.50
2
4
I ds(
)
Vgs
-Vt(V)
25nm
30nm
45nm
50nm
60nm
70nm
100nm
C D
F
Figure S10|Measured electrical properties of small pitch CNT CMOS FETs. Transfer curves of
contact-scaled n-type FETs and p-type FETs based on a CNT with a diameter of 1.5 nm (A, B), and of
1.1 nm (C, D), with contact lengths arranging from 25 nm to 100 nm, and with Vds=±0.1 V.
(E)Transfer and (F) output characteristics of typical small pitch CNT CMOS FETs with Pd and Sc
contact length of approximate 25 nm.
15
Figure S11| Fabrication process flow of a small pitch CNT CMOS inverter.
16
A
Figure S12| Amorphous carbon assisted ALD process for ultra-thin HfO2 on graphene. The
ultra-thin HfO2 on graphene were shown in SEM and AFM images, the thickness is 3.5 nm and
the growth conditions for ALD process are same with 10 nm CNT CMOS gate dielectrics. ALD
of thin films on intrinsic graphene is not easy due to the absence of dangling bonds, so HfO2 can
only be growth on the defects of graphene and was discontinuous (left, A). After deposition a
thin amorphous carbon film which is induced by SEM process (1.5 kV accelerated voltage, 60
um aperture, 8000 magnification), a uniform 3.5 nm HfO2 can be grown on graphene with the
mean roughness of 0.29 nm (right, B), without inducing additional roughness. (The mean
roughness of the intrinsic graphene was about 0.3 nm).
17
Figure S14| Self-aligned graphene-contact CNT FET.
Fig. S13| A contact geometry that combines Side-contacts and End-contacts.
18
Fig. S15| Imaging CNT FETs by SEM with different voltages.
References 1. M. M. Waldrop, The chips are down for Moore’s law. Nature 530, 144–147 (2016).
doi:10.1038/530144a Medline
2. W. M. Holt, in IEEE International Solid-State Circuits Conference (ISSCC), 2016 IEEE International (IEEE, 2016); 10.1109/ISSCC.2016.7417888.
3. M. Lundstrom, Moore’s law forever? Science 299, 210–211 (2003). doi:10.1126/science.1079567 Medline
4. R. K. Cavin, P. Lugli, V. V. Zhirnov, Science and engineering beyond Moore’s law. Proc. IEEE 100, 1720–1749 (2012). doi:10.1109/JPROC.2012.2190155
5. K. J. Kuhn et al., in Electron Devices Meeting (IEDM), 2012 IEEE International (IEEE, 2012); 10.1109/IEDM.2012.6479001.
6. L. Chang, Y.-K. Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, C. Hu, T.-J. King, Extremely scaled silicon nano-CMOS devices. Proc. IEEE 91, 1860–1873 (2003). doi:10.1109/JPROC.2003.818336
7. M. Luisier et al., in International Electron Devices Meeting (IEDM), 2012 IEEE International (IEEE, 2012); 10.1109/IEDM.2011.6131531.
8. G. S. Tulevski, A. D. Franklin, D. Frank, J. M. Lobez, Q. Cao, H. Park, A. Afzali, S.-J. Han, J. B. Hannon, W. Haensch, Toward high-performance digital logic technology with carbon nanotubes. ACS Nano 8, 8730–8745 (2014). doi:10.1021/nn503627h Medline
9. L. M. Peng, Z. Y. Zhang, S. Wang, Carbon nanotube electronics: Recent advances. Mater. Today 17, 433–442 (2014). doi:10.1016/j.mattod.2014.07.008
10. A. Javey, J. Guo, Q. Wang, M. Lundstrom, H. Dai, Ballistic carbon nanotube field-effect transistors. Nature 424, 654–657 (2003). doi:10.1038/nature01797 Medline
11. Z. Y. Zhang, X. Liang, S. Wang, K. Yao, Y. Hu, Y. Zhu, Q. Chen, W. Zhou, Y. Li, Y. Yao, J. Zhang, L.-M. Peng, Doping-free fabrication of carbon nanotube based ballistic CMOS devices and circuits. Nano Lett. 7, 3603–3607 (2007). doi:10.1021/nl0717107
12. A. Javey, H. Kim, M. Brink, Q. Wang, A. Ural, J. Guo, P. McIntyre, P. McEuen, M. Lundstrom, H. Dai, High-kappa dielectrics for advanced carbon-nanotube transistors and logic gates. Nat. Mater. 1, 241–246 (2002). doi:10.1038/nmat769 Medline
13. A. Javey, J. Guo, D. B. Farmer, Q. Wang, E. Yenilmez, R. G. Gordon, M. Lundstrom, H. Dai, Self-aligned ballistic molecular transistors and electrically parallel nanotube arrays. Nano Lett. 4, 1319–1322 (2004). doi:10.1021/nl049222b
14. Z. Zhang, S. Wang, L. Ding, X. Liang, T. Pei, J. Shen, H. Xu, Q. Chen, R. Cui, Y. Li, L.-M. Peng, Self-aligned ballistic n-type single-walled carbon nanotube field-effect transistors with adjustable threshold voltage. Nano Lett. 8, 3696–3701 (2008). doi:10.1021/nl8018802 Medline
15. Z. Zhang, S. Wang, Z. Wang, L. Ding, T. Pei, Z. Hu, X. Liang, Q. Chen, Y. Li, L.-M. Peng, Almost perfectly symmetric SWCNT-based CMOS devices and scaling. ACS Nano 3, 3781–3787 (2009). doi:10.1021/nn901079p Medline
16. L. Ding, Z. Zhang, S. Liang, T. Pei, S. Wang, Y. Li, W. Zhou, J. Liu, L.-M. Peng, CMOS-based carbon nanotube pass-transistor logic integrated circuits. Nat. Commun. 3, 677 (2012). doi:10.1038/ncomms1682 Medline
17. A. D. Franklin, S. O. Koswatta, D. B. Farmer, J. T. Smith, L. Gignac, C. M. Breslin, S.-J. Han, G. S. Tulevski, H. Miyazoe, W. Haensch, J. Tersoff, Carbon nanotube complementary wrap-gate transistors. Nano Lett. 13, 2490–2495 (2013). doi:10.1021/nl400544q Medline
18. A. D. Franklin, Z. Chen, Length scaling of carbon nanotube transistors. Nat. Nanotechnol. 5, 858–862 (2010). doi:10.1038/nnano.2010.220 Medline
19. A. D. Franklin, M. Luisier, S.-J. Han, G. Tulevski, C. M. Breslin, L. Gignac, M. S. Lundstrom, W. Haensch, Sub-10 nm carbon nanotube transistor. Nano Lett. 12, 758–762 (2012). doi:10.1021/nl203701g Medline
20. C. G. Qiu, Z. Zhang, Y. Yang, M. Xiao, L. Ding, L.-M. Peng, Exploration of vertical scaling limit in carbon nanotube transistors. Appl. Phys. Lett. 108, 193107 (2016). doi:10.1063/1.4949336
21. A. D. Franklin et al., in International Electron Devices Meeting (IEDM), 2012 IEEE International (IEEE, 2012); 10.1109/IEDM.2012.6478979.
22. S. Natarajan et al., in International Electron Devices Meeting (IEDM), 2014 IEEE International (IEEE, 2014); 10.1109/IEDM.2014.7046976.
23. C. Auth et al., in Symposium on VLSI Technology, 2012 IEEE International (IEEE, 2012); 10.1109/VLSIT.2012.6242496.
24. N. Patil, J. Deng, S. Mitra, H.-S. P. Wong, Circuit-level performance benchmarking and scalability analysis of carbon nanotube transistor circuits. IEEE Trans. Nanotechnol. 8, 37–45 (2009). doi:10.1109/TNANO.2008.2006903
25. A. D. Franklin, Electronics: The road to carbon nanotube transistors. Nature 498, 443–444 (2013). doi:10.1038/498443a Medline
26. C. Qiu, Z. Zhang, D. Zhong, J. Si, Y. Yang, L.-M. Peng, Carbon nanotube feedback-gate field-effect transistor: Suppressing current leakage and increasing on/off ratio. ACS Nano 9, 969–977 (2015). doi:10.1021/nn506806b Medline
27. E. Ungersboeck, M. Pourfath, H. Kosina, A. Gehring, B.-H. Cheong, W.-J. Park, S. Selberherr, Optimization of single-gate carbon-nanotube field-effect transistors. IEEE Trans. Nanotechnol. 4, 533–538 (2005). doi:10.1109/TNANO.2005.851402
28. C. S. Lee, E. Pop, A. D. Franklin, W. Haensch, H. S. P. Wong, A compact virtual-source model for carbon nanotube FETs in the sub-10-nm regime—part II: Extrinsic elements, performance assessment, and design optimization. IEEE Trans. Electron Dev. 62, 3070–3078 (2015). doi:10.1109/TED.2015.2457424
29. Z. Yao, C. L. Kane, C. Dekker, High-field electrical transport in single-wall carbon nanotubes. Phys. Rev. Lett. 84, 2941–2944 (2000). doi:10.1103/PhysRevLett.84.2941 Medline
30. J. Y. Park, S. Rosenblatt, Y. Yaish, V. Sazonova, H. Üstünel, S. Braig, T. A. Arias, P. W. Brouwer, P. L. McEuen, Electron-phonon scattering in metallic single-walled carbon nanotubes. Nano Lett. 4, 517–520 (2004). doi:10.1021/nl035258c
31. F. Léonard, D. A. Stewart, Properties of short channel ballistic carbon nanotube transistors with ohmic contacts. Nanotechnology 17, 4699–4705 (2006). doi:10.1088/0957-4484/17/18/029 Medline
32. S. Heinze, J. Tersoff, R. Martel, V. Derycke, J. Appenzeller, P. Avouris, Carbon nanotubes as Schottky barrier transistors. Phys. Rev. Lett. 89, 106801 (2002). doi:10.1103/PhysRevLett.89.106801 Medline
33. S. Migita et al., in International Electron Devices Meeting (IEDM), 2012 IEEE International (IEEE, 2012); 10.1109/IEDM.2012.6479006.
34. H. Lee et al., in Symposium on VLSI Technology, 2006 IEEE International (IEEE, 2006); 10.1109/VLSIT.2006.1705215.
35. A. W. Cummings, F. Léonard, Enhanced performance of short-channel carbon nanotube field-effect transistors due to gate-modulated electrical contacts. ACS Nano 6, 4494–4499 (2012). doi:10.1021/nn301302n Medline
36. S. J. Choi, P. Bennett, K. Takei, C. Wang, C. C. Lo, A. Javey, J. Bokor, Short-channel transistors constructed with solution-processed carbon nanotubes. ACS Nano 7, 798–803 (2013). doi:10.1021/nn305277d Medline
37. R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, M. Radosavljevic, Benchmarking nanotechnology for high-performance and low-power logic transistor applications. IEEE Trans. Nanotechnol. 4, 153–158 (2005). doi:10.1109/TNANO.2004.842073
38. B. Yu et al., in 2002 IEEE International (IEEE, 2002); 10.1109/IEDM.2002.1175825.
39. International Technology Roadmap for Semiconductors (2013 edition); http://public.itrs.net/.
40. W. Haensch, E. J. Nowak, R. H. Dennard, P. M. Solomon, A. Bryant, O. H. Dokumaci, A. Kumar, X. Wang, J. B. Johnson, M. V. Fischetti, Silicon CMOS devices beyond scaling. IBM J. Res. Develop. 50, 339–361 (2006). doi:10.1147/rd.504.0339
41. J. D. Meindl, Q. Chen, J. A. Davis, Limits on silicon nanoelectronics for terascale integration. Science 293, 2044–2049 (2001). doi:10.1126/science.293.5537.2044 Medline
42. A. D. Franklin, D. B. Farmer, W. Haensch, Defining and overcoming the contact resistance challenge in scaled carbon nanotube transistors. ACS Nano 8, 7333–7339 (2014). doi:10.1021/nn5024363 Medline
43. Q. Cao, S.-J. Han, J. Tersoff, A. D. Franklin, Y. Zhu, Z. Zhang, G. S. Tulevski, J. Tang, W. Haensch, End-bonded contacts for carbon nanotube transistors with low, size-independent resistance. Science 350, 68–72 (2015). doi:10.1126/science.aac8006 Medline
44. W. Zhou, Z. Han, J. Wang, Y. Zhang, Z. Jin, X. Sun, Y. Zhang, C. Yan, Y. Li, Copper catalyzing growth of single-walled carbon nanotubes on substrates. Nano Lett. 6, 2987–2990 (2006). doi:10.1021/nl061871v Medline
45. J. Xiao, S. Dunham, P. Liu, Y. Zhang, C. Kocabas, L. Moh, Y. Huang, K.-C. Hwang, C. Lu, W. Huang, J. A. Rogers, Alignment controlled growth of single-walled carbon nanotubes on quartz substrates. Nano Lett. 9, 4311–4319 (2009). doi:10.1021/nl9025488 Medline
46. Y. Che, Y. C. Lin, P. Kim, C. Zhou, T-gate aligned nanotube radio frequency transistors and circuits with superior performance. ACS Nano 7, 4343–4350 (2013). doi:10.1021/nn400847r Medline
47. Z. Wang, H. Xu, Z. Zhang, S. Wang, L. Ding, Q. Zeng, L. Yang, T. Pei, X. Liang, M. Gao, L.-M. Peng, Growth and performance of yttrium oxide as an ideal high-kappa gate dielectric for carbon-based electronics. Nano Lett. 10, 2024–2030 (2010). doi:10.1021/nl100022u Medline