Post on 02-Jan-2016
SimArch: SimArch: Work in ProgressWork in Progress
Multimedia Teaching Tool
Faculty of Electronic Engineering
University of Nis
Serbia
2/23
OutlineOutline
SimArch, motivation and application area SimArch v.1.0, system and user view Work in progress
3/23
SimArch is a teaching tool that supports lectures of computer architectures.
Basic package distribution contains files with RISC architectures that are involved in computer architecture courses at Faculty of Electronic Engineering, University of Nis.
Flexibility allows SimArch to meet requirements of any computer architecture course.
SimArch - Application areaSimArch - Application area
4/23
MotivationMotivation
Need for a visualization tool that leads to higher quality lectures.– less time spent on drawing
= more time for talk (explanation, discussion)
– "Live" hardware presentation (step-by-step data flow) = better lecture understanding
PowerPoint
PowerPoint
5/23
Software requirementsSoftware requirements FUNCTIONAL REQUIREMENTS
Visualization of custom processor architecture. Hardware descriptions have to be stored in separate files. Capabilities of viewing hardware component details. Visualization of instruction flow through processor
components. Detailed information of hardware components status need
to be derived from actual hardware simulation. Flexibility that enables easy involving of new lectures. User-friendly interface. Easy software upgrading.
Visualization of custom processor architecture.
Detailed information of hardware components status need to be derived from actual hardware simulation.
Flexibility that enables easy involving of new lectures.
6/23
Software requirementsSoftware requirements
NON-FUNCTIONAL REQUIREMENTS
Graphical elements optimized for presentation using video-beam.
Supported platforms: Microsoft Win9x, Win2000, WinXP.
7/23
Development environmentDevelopment environment
CASE tools that have been used for software development are:
Rational Rose 2000e (UML notation), Microsoft Visual Studio 6.0 (Visual C++).
8/23
Used techniques Used techniques
Involved requirement complexity demands the usage of Design Patterns as well as an involvement of some task-separation techniques.
Used Design Patterns: Singleton classes Manager classes Interface classes
9/23
Software model Software model
SimArch contains a few sub-systems. Sub-systems are
Components Engine Window Manager Draw Manager Shared Components
11/23
Script language Script language
A specialized, custom script language has been developed to meet requirements of lecture description. Script language consists of three different notations:
Script file for hardware description, Lecture scenario description, Pseudo-assembler language.
12/23
Script exampleScript example <Architecture description>
PC(0,1;2) %38 ?28,302,29,60,1OR#3(7,93;1) %1 ?30,100,26,26,1CONSTANT#1(;3) %4 ?80,238,0,0,1ADD#1(2,3;4) ?110,185,35,80,1INSTRUCTION_MEMORY(2;5) %.\Code\Code.mps ?
85,302,69,125,1IF_ID(5,4,6,7;8,9) ?175,217,22,330,1BUS_SPLITER#1(8;57) %31,26 ?0,0,0,0,0…#INSTRUCTION=ADDPCINSTRUCTION_MEMORYADD#1CONSTANT#1MUX2X1#17MUX2X1#182-12-23-14-15-187-10-1stop
<Assembler code example>30: sw $25, 50($7)34: j 1638: lw $10, 0($1)3c: add $8, $10, $840: sub $11, $2, $344: lw $16, -12($7)48: and $12, $1, $74c: or $13, $1, $750: add $1, $2, $154: slt $12, $15, $658: beq $3, $9, -115c: slt $3, $0, $160: or $2, $3, $564: sub $1, $2, $25
<Scenario description>
.\1_Singleclock implementation\Single.shm
.\2_Multiclock implementation\Multi.shm
.\3_Pipeline without Forwarding\Main.shm
.\3_Pipeline without Forwarding\Main_HDU.shm
.\4_Pipeline with Forwarding\Main.shm
.\4_Pipeline with Forwarding\Main_FU_HDU.shm
13/23
How to use SimArch?How to use SimArch?
Lectures are being prepared by the following steps:
Step 1: Architecture selection Step 2: Planning the lecture flow Step 3: Scripts writing.
14/23
How to use SimArch?How to use SimArch?
Presentation conduction consists of two steps:
Step 1: Selection and loading of created script Step 2: Step-by-step presentation driven by the script.
16/23
Work in progressWork in progress
Moving components descriptions to user level
Expanding of Component Library Architecture draw tool
17/23
Work in progressWork in progress
Moving components descriptions to user level
In v.1.0 components descriptions – C++ functions, embedded in source code
We want to allow users to add/change components without compilation of entire program
VHDL as a native language for HW description is chosen
Teachers may use descriptions they already posses Usage of external simulator
18/23
Work in progressWork in progress
Moving components descriptions to user level
Implementation: Connection with Symphony EDA VHDL Simili
v2.1 Free edition Simili simulates components (not entire
architecture)
19/23
Work in progressWork in progress
Moving components descriptions to user levelS cen ar io .s ce
Single . shm Multi . shm
Add . vhd Add . vhd
ALU . vhd
Ctrl . vhd
CodeS.mps CodeM.mps
MemoryS.mps MemoryM.mps
RegistersS.mps RegistersM.mps
SimArch Similii
- load components
S cen ar io .s ce
Single . shm Multi . shm
TB _A d d . v h d
Add . vhd
ALU . vhd
Ctrl . vhd
CodeS.mps CodeM.mps
MemoryS.mps MemoryM.mps
RegistersS.mps RegistersM.mps
SimArch Similii
- load components
- testbenches
S cen ar io .s ce
Single . shm Multi . shm
Add . vhd
ALU . vhd
Ctrl . vhd
CodeS.mps CodeM.mps
MemoryS.mps MemoryM.mps
RegistersS.mps RegistersM.mps
- load components
- testbenches
Add . vhd
A d d . v h d
E n t i ty a d d i s
p o rt ( in 1 , i n 2 : i n b it _ v e c t o r (3 1 d o w n t o 0 ) ;
o u t 0 : o u t b i t_ v e c to r (3 1 d o w n t o 0 ) ;
c O : o u t b it );
e n d e n t it y a d d
a rc h i te c t u re a d d _ a r c h o f a d d is
A d d . v h d
E n t i ty a d d i s
p o rt ( in 1 , i n 2 : i n b it _ v e c t o r (3 1 d o w n t o 0 ) ;
o u t 0 : o u t b i t_ v e c to r (3 1 d o w n t o 0 ) ;
c O : o u t b it );
e n d e n t it y a d d
a rc h i te c t u re a d d _ a r c h o f a d d is
S cen ar io .s ce
Single . shm Multi . shm
TB _A d d . v h d
Add . vhd
ALU . vhd
Ctrl . vhd
CodeS.mps CodeM.mps
MemoryS.mps MemoryM.mps
RegistersS.mps RegistersM.mps
SimArch Similii
- load components
- testbenches
S cen ar io .s ce
Single . shm Multi . shm
Add . vhd
ALU . vhd
Ctrl . vhd
CodeS.mps CodeM.mps
MemoryS.mps MemoryM.mps
RegistersS.mps RegistersM.mps
- load components
- testbenches
Add . vhd
A d d . v h d
E n t i ty a d d i s
p o rt ( in 1 , i n 2 : i n b it _ v e c t o r (3 1 d o w n t o 0 ) ;
o u t 0 : o u t b i t_ v e c to r (3 1 d o w n t o 0 ) ;
c O : o u t b it );
e n d e n t it y a d d
a rc h i te c t u re a d d _ a r c h o f a d d is
A d d . v h d
E n t i ty a d d i s
p o rt ( in 1 , i n 2 : i n b it _ v e c t o r (3 1 d o w n t o 0 ) ;
o u t 0 : o u t b i t_ v e c to r (3 1 d o w n t o 0 ) ;
c O : o u t b it );
e n d e n t it y a d d
a rc h i te c t u re a d d _ a r c h o f a d d is
- simulation
S cen ar io .s ce
Single . shm Multi . shm
TB _A d d . v h d
Add . vhd
ALU . vhd
Ctrl . vhd
CodeS.mps CodeM.mps
MemoryS.mps MemoryM.mps
RegistersS.mps RegistersM.mps
SimArch Similii
- load components
- testbenches
S cen ar io .s ce
Single . shm Multi . shm
Add . vhd
ALU . vhd
Ctrl . vhd
CodeS.mps CodeM.mps
MemoryS.mps MemoryM.mps
RegistersS.mps RegistersM.mps
- load components
- testbenches
Add . vhd
A d d . v h d
E n t i ty a d d i s
p o rt ( in 1 , i n 2 : i n b it _ v e c t o r (3 1 d o w n t o 0 ) ;
o u t 0 : o u t b i t_ v e c to r (3 1 d o w n t o 0 ) ;
c O : o u t b it );
e n d e n t it y a d d
a rc h i te c t u re a d d _ a r c h o f a d d is
A d d . v h d
E n t i ty a d d i s
p o rt ( in 1 , i n 2 : i n b it _ v e c t o r (3 1 d o w n t o 0 ) ;
o u t 0 : o u t b i t_ v e c to r (3 1 d o w n t o 0 ) ;
c O : o u t b it );
e n d e n t it y a d d
a rc h i te c t u re a d d _ a r c h o f a d d is
- simulation
out0=X“180DC0”cO = 0
S cen ar io .s ce
Single . shm Multi . shm
TB _A d d . v h d
Add . vhd
ALU . vhd
Ctrl . vhd
CodeS.mps CodeM.mps
MemoryS.mps MemoryM.mps
RegistersS.mps RegistersM.mps
SimArch Similii
- load components
- testbenches
S cen ar io .s ce
Single . shm Multi . shm
Add . vhd
ALU . vhd
Ctrl . vhd
CodeS.mps CodeM.mps
MemoryS.mps MemoryM.mps
RegistersS.mps RegistersM.mps
- load components
- testbenches
Add . vhd
A d d . v h d
E n t i ty a d d i s
p o rt ( in 1 , i n 2 : i n b it _ v e c t o r (3 1 d o w n t o 0 ) ;
o u t 0 : o u t b i t_ v e c to r (3 1 d o w n t o 0 ) ;
c O : o u t b it );
e n d e n t it y a d d
a rc h i te c t u re a d d _ a r c h o f a d d is
A d d . v h d
E n t i ty a d d i s
p o rt ( in 1 , i n 2 : i n b it _ v e c t o r (3 1 d o w n t o 0 ) ;
o u t 0 : o u t b i t_ v e c to r (3 1 d o w n t o 0 ) ;
c O : o u t b it );
e n d e n t it y a d d
a rc h i te c t u re a d d _ a r c h o f a d d is
- simulation
out0=X“180DC0”cO = 0
- results pool
- display
20/23
Work in progress Work in progress
Expanding of Component Library
Easier expanding by VHDL input.
In standard package distribution :CISC processor componentsComponents needed by most of DSP architectures
21/23
Work in progressWork in progress
Architecture draw tool
Architecture layout description is in script file – inconvenient (Hard work to adjust manually)
We are designing a tool for visual creation of script file, similar to Block Diagram tools that can be found in commercial products
23/23
ConclusionConclusion
Recent developments of SimArch have been presented.
Future work will be focused on – Client-server functionality– Web version of the application– Further improvements of the interface and
visualization.