Post on 30-Mar-2015
Senior Capstone Project:Fast Tuning Synthesizer
Member: Nathan RothAdvisors: Dr. Huggins
Dr. ShastryMr. James Jensen
Date: December 9, 2003
Presentation Outline
• Project Summary
• Standards and Patents
• Functional Description
• Detailed Description
• Preliminary Laboratory Work/Results
• Preliminary Bill of Materials
• Preliminary Spring Semester Schedule
Project Summary
• Creation of a frequency synthesizer– Use of direct synthesis approach
• Design of synthesizer using indirect synthesis– Use of phase-locked loops
Project Summary
• Desired Characteristics– Output Frequency Range of 3.4 GHz to 4.6
GHz – Step Size of 50 MHz– Output Power of 0 dBm, ± 3 dB– Output Spurs < -45 dBc– Tuning Time < 500 ns, 200 ns if possible– Use of an External 100 MHz Reference Signal
Project Summary
• Actual Characteristics– Output Frequencies of 3650, 3700, 3850,
3900, 4450, 4500, 4650, and 4700 MHz– Output Power of 0 dBm, ± 3 dB– Output Spurs < -45 dBc– Tuning Time < 500 ns, 200 ns if possible– Use of an External 100 MHz Reference Signal
Standards
• Standards– Depends Upon Application– C, X, and KU Band Channels:
• MIL-STD-188-164
– Military Satellite Communications (MILSATCOM):
• MIL-STD-188-166: Interface Standard • MIL-STD-188-167: Message Format • MIL-STD-188-168: Interface for Satellite
Multiplexers and Demultiplexers
Patents
• Patent Number 5,166,629
• Grant Watkins and John Muhlbair of Westinghouse Electric Corporation on November 24, 1992
Functional Description
FastTuning
FrequencySynthesizer
3.6 – 4.6 GHz
100 MHz Reference
D2
D1
D0
Digital Input Command
Desired Output
Frequency
Detailed Description
Input Module
Resolution Modules
Basis Frequency Modules
Switch Selection Module
Output Module
Preliminary Laboratory Work
• Design and Simulation of Ideal Chebyshev Filters
• Currently Adding Parasitic Effects– Real Component Values– Real Inductor Responses– Microstrip Transmission Effects– Via Connections
Preliminary Laboratory Work
• Filter Design– Insertion Loss Method
Preliminary Laboratory Work
• Filter Design
Preliminary Laboratory Work
Preliminary Laboratory Work
Ideal S11 = Dark Blue
Ideal S21 = Aqua Blue
Actual S11 = Red
Actual S21 = Purple
Preliminary Laboratory Work
Preliminary Laboratory Work
Preliminary Bill of MaterialsPart Number Maker Description Qty Price Total
Price
HMC435MS8G Hittite SPDT, Hi Isolation, DC- 4 GHz
15 1.1 16.5
PE3512 Peregrine Divide By 4, DC - 1.5 2 2.75 5.5
MAX2671 Maxim IC 400 MHz To 2.5 GHz Upconverter Mixers
3 0.76 2.28
SYK-2R Mini-Circuits Frequency Doublers, 10-1000 MHz
1 29.95 29.95
HMC188MS8 Hittite Passive Frequency Doubler, 1.25 - 3.0 GHz
Input
1 2.94 2.94
HMC187MS8 Hittite Passive Frequency Doubler, 0.85 - 2.0 GHz
1 2.35 2.35
Preliminary Bill of MaterialsMSA-2743 Agilent Cascadable Silicon Bipolar
Gain Block MMIC Amplifier
1 0.94 0.94
ABA-53563 Agilent 3.5 GHz Broadband Silicon RFIC Amplifier
3 0.4 1.2
HMC315 Hittite GaAs InGaP HBT MMIC Darlington Amplifier,
DC - 7.0 GHz
3 0.97 2.91
AG604-89 WJ Ingap HBT Gain Block 2 1.48 2.96
TK10-KIT-ND Toko 250 Pcs - 10 Ea Of 25 Values
1 40.5 40.5
Substrate Rogers Corporation
RO4003, .020 Mil Thick, 1.4 Mil Foil
2 32.25 64.5
Total 172.53
Preliminary Spring Semester Schedule
Week TaskWinter Break Research and understand phase locked loop
(PLL) theory and circuitry
Begin design of PLL system
Finalize filter design and simulations
Begin implementing as parts arrive
Full scale simulation of direct synthesis (DS) system
Jan 19 – 25 Design of PLL system
DS system simulation
Jan 26 – Feb 1 Design PLL system
DS system simulation
Have all filters tested and built
Feb 2 – 8 Complete design of PLL system
DS system simulation
Feb 9 – 15 Simulation of PLL system
Complete DS system Simulation
Preliminary Spring Semester Schedule
Feb 9 – 15 Simulation of PLL system
Complete DS system Simulation
Feb 16 – 22 Simulation of PLL system
Feb 23 – 29 Complete simulation of PLL system
March 1 – 7 Components Arrive, Begin Soldering, Testing, and Biasing Components
March 8 – 14 Physical implementation of DS
March 15 – 21 Physical implementation of DS, Spring Break?
March 22 – 28 Begin DS full scale testing
March 29 – April 4 DS full scale testing
April 5 – 11 Complete DS full scale testing
April 12 – 18
April 19 – 25 Student Expo
April 26 – May 2 Present successful findings
Fast Tuning Synthesizer
• Any questions?