How to run a Modelsim using TCL script

Aneesh Raveendran Centre For Development of Advanced Computing Bangalore, India

How to run a ModelSim using TCL script

Once you completed the HDL coding in ModelSim or any text editor with file extension ‘.vhd’for VHDL and ‘ .vo’ for Verilog then, we can use TCL script to run the entire project .

For example I have a vhdl file of name “full_adder.vhd” and write a test bench to run the full adder with name “tb_full_adder.vhd”.we will check how this TCL work for this project.

TCL script is

vlib work

vmap work

vcom full_adder.vhd

vcom tb_full_adder.vhd

vsim tb_full_adder

add wave -radix decimal -r /*

run 1 ms

Explanation

Vlib work � Creates a library with name work

Vmap work � Mapping all the design units into work

Vcom full_adder.vhd � Compile the full adder design unit

Vcom tb_full_adder.vhd � Compile the test bench for the full adder

Vsim tb_full_adder �Simulate the test bench for the full adder (don’t add the file extension)

add wave -radix decimal -r /* � Adding all the signals to the wave window

run 1 ms � Running the full adder design unit to 1 ms with test bench that you write

if you found any difficulty in executing the TCL script please drop a mail to me

aneeshr2020@gmail.com