Electrical  Characteriza-on  and  Test  

Pull-­‐In/Pull-­‐Out  Voltage  

Measuring  Actua-on  Delay  

Pull-­‐in/Pull-­‐out  Voltage  

Reliability  Tes-ng  

MOCVD  TiN-­‐Coated  Polysilicon  

Procedure:  1.  Bias  drain  and  ground  source  (beam)  2.  Increase  the  applied  gate  voltage  

(quasi-­‐sta=c  ramp)  un=l  drain  current  increases  sharply,  indica=ng  pull-­‐in.  

3.  Ramp  gate  voltage  back  down  to  zero.  Pull-­‐out  occurs  when  drain  current  drops  below  noise  floor.  

All   tes'ng   is   performed   in   a   controlled  N2   glovebox   probe   sta'on   to   protect  samples   against   degrada'on   due   to  ambient  moisture.  

Procedure:  1.  Apply  a  square  pulse  of  magnitude  >VPI  to  the  gate.  

 *Variable  parameters:  rise/fall  sharpness,  pulse  width  

2.  Possible  outcomes  a)  If  device  fails,  drain  voltage  VD  remains  at  zero.  b)  If  device  actuates,  drain  voltage  VD  approaches  

the  source  bias  VS.  The  resul=ng  plot  allows  us  to  calculate  mechanical  delay,  actua=on  =me,  and  contact  resistance.  

Time (s)

Gate/Drain Voltage (V)

Mechanical Delay

Pull-In Voltage (VPI)

100

200

0

300

600

500

400

Mechanical Delay (ns)

Ini-alize  

Apply  gate  pulse  

Did  switching  occur?  

Pulse  N  -mes   End  test  

Yes No

Image  Credit:  Soogine  Chong  (Reliability  tes=ng)  

-­‐5  

0  

5  

10  

15  

20  

25  

0   10   20   30   40   50  

Drain  Current  (n

A)  

Gate  Voltage  (V)  

Hysteresis  

Pull-­‐in  

Pull-­‐out  

Joel  Jean  jjean@stanford.edu  

Srikanth  Iyer  ssiyer@stanford.edu  

MOSFET-­‐Killer:  Nanoelectromechanical  (NEM)  Relays  for  Low-­‐Power  Logic  Joel  Jean,  Srikanth  Iyer,  W.  ScoT  Lee,  Roger  Howe  

Abstract  To   con=nue   the   trend   of   increasingly   powerful,   smaller,   and   cheaper   consumer   electronic  

devices   and   to   keep  up  with   the   self-­‐fulfilling   prophecy  of  Moore’s   Law,   silicon-­‐based  metal-­‐oxide-­‐semiconductor  field  effect   transistors   (MOSFETs)  have  been   con=nually   scaled  down   in   size   for   the  last  several  decades.  The  advantages  of  scaling  are  many:  Smaller  devices  consume  less  power,  have  improved   current   drive   and   frequency   response,   and   enable   increased   device   packing   density,  resul=ng   in   lower  fabrica=on  cost  per  chip.   In  decreasing  the  dimensions  of  MOSFETs,  however,  we  find   that   transistor   leakage   currents––from   gate   oxide   tunneling,   drain-­‐induced   barrier   lowering  (DIBL),   and   band-­‐to-­‐band   tunneling   (BTBT)––correspond   to   an   increasingly   large   propor=on   of   the  total   power   consump=on.   The  MOSFET’s   fundamentally-­‐limited   subthreshold   slope   precludes   low-­‐power  logic  based  on  exis=ng  CMOS  technologies.  

In   the   current   research,   we   explore   nanoelectromechanical  (NEM)  relays  as  a  poten=al   replacement   for  MOSFETs   in   low-­‐power  applica=ons,   such   as   mobile   devices   and   sensors,   and   as   sleep  transistors   in   both   FPGAs   and  ASICs.  We  have   performed   electrical  characteriza=on,   iden=fied   common   failure   mechanisms,   and  conducted   dynamic   (switching   =me   and   pulse)  measurements   of   a  variety   of   microfabricated   NEM   relay   structures   in   a   nitrogen  glovebox  test  environment.  Our  future  work  will  involve  inves=ga=on  of   energy   recovery   (ER)   techniques   for   lowering   dynamic   power  consump=on,   durability   tes=ng,   and   implementa=on   of   logic  func=ons.   Ul=mately,   the   near-­‐ideal   switching   behavior   of  electrosta=cally   actuated   NEM   relays––negligible   off-­‐current   and  near-­‐infinite   subthreshold   slope––and   compa=bility   with   exis=ng  CMOS   fabrica=on   technologies   offer   a   promising   route   to   longer  baTery   life   and   increased   performance   in   tomorrow’s   consumer  electronics.  

Failure  Mechanisms  

S-c-on  

Pull-­‐In  to  Gate  

Beam  Curling   Explosion  

When   the   beam   is   too   flexible,   it  may  touch   the   gate   before   pulling   into   the  drain.   At   high   poten=als,   this   contact  can  destroy  fragile  beams.    

ATrac=ve   surface   forces   (i.e.,   van  der  Waals)  dominate  at  close  range:  Acer  actua=on,  adhesive  force  between  the  beam   and   drain   some=mes   exceeds  the  mechanical   restoring   force  of   the  beam,  and  the  beam  fails   to  pull  out.  S=c=on   is   exacerbated  by  overdriving  the   gate   pulse   and   passing   high  current  through  the  beam  and  drain.  

Relay  Design  and  Opera-on  

Device  Layout  and  Fabrica-on  

Electrosta-c  Actua-on  

Drain    

Beam  

+  –  VGS  

Gate    Source    

Beam

Gate 1 Gate 2

Drain 1 Drain 2

g b

s

d o

w

MOCVD  TiN  Stringer  

TiN  Sidewall  Stringer  

Image  Credit:  Roozbeh  Parsa  (Electrosta=c  schema=c),  Kyeongran  Yoo  (5T  device  parameters)  

Future  Work  &  Applica-ons  

FPGA  Rou-ng  Switches  

Energy  Recovery  (ER)  Tes-ng  

In   applica=ons   where   the   device  alternates   between   lec   and   right  actua=on,  we  can  use  a  5-­‐terminal  relay   to   reduce   dynamic   power  consump=on   by   taking   advantage  of  the  restoring  momentum  of  the  beam.   While   the   beam   is   pulling  out   from   one   side,   the   pull-­‐in  voltage   on   the   other   side   is  effec=vely  decreased.  

Image  Credit:  Chen  Chen  (FPGA  data)