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Research ArticleEnhanced Device and Circuit-Level PerformanceBenchmarking of Graphene Nanoribbon Field-Effect Transistoragainst a Nano-MOSFET with Interconnects
Huei Chaeng Chin,1 Cheng Siong Lim,1 Weng Soon Wong,1
Kumeresan A. Danapalasingam,1 Vijay K. Arora,1,2 and Michael Loong Peng Tan1
1 Faculty of Electrical Engineering, Universiti Teknologi Malaysia (UTM), 81310 Skudai, Johor, Malaysia2 Division of Engineering and Physics, Wilkes University, Wilkes-Barre, PA 18766, USA
Correspondence should be addressed to Michael Loong Peng Tan; michael@fke.utm.my
Received 10 December 2013; Revised 11 February 2014; Accepted 12 February 2014; Published 26 March 2014
Academic Editor: Tianxi Liu
Copyright Β© 2014 Huei Chaeng Chin et al. This is an open access article distributed under the Creative Commons AttributionLicense, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properlycited.
Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET) and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET) for applications in ultralarge-scale integration (ULSI) is reported. GNRFETis found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into analternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nmprocess technology.The assessment ofthese performance metrics includes energy-delay product (EDP) and power-delay product (PDP) of inverter and NOR and NANDgates, forming the building blocks for ULSI.The evaluation of EDP and PDP is carried out for an interconnect length that ranges upto 100 πm. An analysis, based on the drain and gate current-voltage (πΌπ-ππ and πΌπ-ππ), for subthreshold swing (SS), drain-inducedbarrier lowering (DIBL), and current on/off ratio for circuit implementation is given. GNRFET can overcome the short-channeleffects that are prevalent in sub-100 nm Si MOSFET. GNRFET provides reduced EDP and PDP one order of magnitude that islower than that of a MOSFET. Even though the GNRFET is energy efficient, the circuit performance of the device is limited by theinterconnect capacitances.
1. Introduction
The number of transistors on a typical 1 Γ 1 cm chip hasgrown exponentially with twofold increase every 18 monthskeeping Mooreβs Law [1] on track. Serious hindrances arein sight as transistor scaling enters the nanometer domain.Short-channel effects are significant as devices are scaledbelow sub-100 nm, providing challenges and opportunitiesfor device and process engineers. Researchers across theglobe are exploring new nanomaterials with transformedarchitecture to circumvent the roadblocks of silicon-basednanotechnology for enhanced circuit performance. Inter-connects also play a key role as channels reach nanometerscale and resistance surge takes on an increasing impor-tance [2]. Carbon-based allotropes offer a distinct advantage
in a variety of applications [3β8]. Graphene nanoribbons(GNRs) are one-dimensional (1D) nanostructures restrictingcarrier motion in only one direction, reducing scattering forenhanced mobility [6, 9]. The transistor current is quite highas electrons are injected from the source and transit to thedrain terminal [6, 10β12]. A narrow width semiconductingGNR is utilized as a channel in a top-gated transistor [13β15]. This pushes the limits of complementary metal-oxide-semiconductor (CMOS) type of technology beyond its limitsin a GNR. This paper focuses on modeling, simulation,and benchmarking of top-gated graphene nanoribbon field-effect transistors (GNRFETs) against MOSFET. In addition,the evaluation of logic performance is carried out for bothdevices. It is observed that there is a good agreement betweenGNRFET and MOSFET based on the drain current-voltage
Hindawi Publishing CorporationJournal of NanomaterialsVolume 2014, Article ID 879813, 14 pageshttp://dx.doi.org/10.1155/2014/879813
2 Journal of Nanomaterials
Table 1: Design specifications C and S for various channel lengths.
Channel length (nm) C (nm) S (nm) W (nm)16 30 8 4632 50 16 8245 60 20 10065 90 40 17090 120 50 220180 220 100 420
(πΌ-π) characteristics. The energy-delay product (EDP) andpower-delay product (PDP) are the performancemetrics thatrepresent the energy efficiencies of GNRFET and MOSFETlogic gates. The simulations in this work are carried outfor the 16 nm manufacturing processes. In the following,device model framework of our previous work [7, 16β19] isextended for the simulation and analysis of GNRFET andMOSFET at 16 nm node. Circuit-level models of GNRFETare benchmarked against MOSFET. Logic performances ofcarbon and silicon-based inverter andNAND andNOR gatesare assessed. For a fair assessment, the same channel length,πΏ = 16 nm, is adopted for GNRFET, PMOS, and NMOS.The device modeling is carried out in MATLAB and circuitdevelopment and simulation is performed usingHSPICE andCosmoscope.
2. Device Modeling
The simulated silicon MOSFET is based on Berkeley short-channel IGFETmodel (BSIM) which was the standardmodelfor deep submicron CMOS circuit design in the early 2000s[20]. IC companies including Intel, IBM, AMD, NationalSemiconductor, and Samsung widely use the charge-basedmodel as an electronic computer-aided design (ECAD) tool.BSIM4 version 4.7 MOSFET model is utilized in the simu-lation of NMOS and PMOS [21] in the present assessment.The top view of GNRFET with source and drain contacts isdepicted in Figure 1. Various values of πΆ and π (see Figure 2)are given in Table 1.
3. Proposed Layout and Design
The interpolated contact size πΆ and spacer size π of16 nm node process technology are illustrated in Figures2(a) and 2(b), respectively.
The channel width,π, is a function of πΆ and S as givenby
π = πΆ + 2π. (1)
Table 1 gives design specifications for channel lengthsfrom 16 to 180 nm range.
4. Analytical Modeling of GNRFET
In this section, the analytical model of GNRFET is derived.The channel surface potential πSC, or self-consistent voltageas is commonly known, is solved numerically in MATLAB
using Newton-Raphson algorithm to obtain the voltagepotential at the top barrier along the channel [23]. The πSCis given by
πSC = ππΏ + ππ =βππ‘ + Ξπ
πΆΞ£
, (2)
where πΆΞ£ is the total sum of capacitance at all the fourterminals and ππ‘ is the total charge. Ξπ is the additionalcharge due to the increase ofπSC.ππΏ is the potential appearingacross the channel region and ππ is existing across theparasitic regions.The other symbols in (2) are given as followswhere ππ is the density of positive velocity states, ππ is thedensity of negative velocity states and π0 is the electrondensity at equilibrium:
ππ‘ = πΆπ ππ + πΆπππ + πΆπππ + πΆsubπsub,
πΆΞ£ = πΆπ + πΆπ + πΆπ + πΆsub,
Ξπ = π (ππ + ππ + π0) .
(3)
The carriers obey the Fermi-Dirac probability distribution asfollows:
ππ =1
2β«
+β
ββ
π· (πΈ)π (πΈ β πSF) ππΈ,
ππ =1
2β«
+β
ββ
π· (πΈ)π (πΈ β πDF) ππΈ,
π0 = β«
+β
ββ
π· (πΈ)π (πΈ β πΈπΉ) ππΈ,
(4)
where πSF and πDF are defined as
πSF = πΈπΉ β ππSC,
πDF = πΈπΉ β ππSC β πππ.(5)
The one-dimensional (1D) density of state (DOS) function in(4) is defined as
π· (πΈ) =2πVππ
3ππccπ‘β
π
πΈ
βπΈ2 β (πΈπΊ/2)2
, (6)
where πcc = 0.142 nm is the CβC bond length and π‘ = 3 eVis the CβC bonding energy. In (6), πΈπΊ is the bandgap energy,ππ is the spin degeneracy, and πV is the valley degeneracy. Inan armchair GNR (aGNR), πV = 1. A nonlinear regressionmodel of πSC is obtained through the use of the polynomialfit [24, 25].The nonlinear approximation forπSC dependenceonππ andππ in the form of fifth-order polynomial is given toreplace theNewton-Raphson algorithm in (2).The regressionmodel is given as
πSC (ππ, ππ) = π΄ππ + π΅ππ5+ πΆππ
4
+ π·ππ3+ πΈππ
2+ πΉππ + πΊ,
(7)
where π΄, π΅, πΆ, π·, πΈ, πΉ, and πΊ are the coefficients extractedfromMATLAB curve fitting tool.
Journal of Nanomaterials 3
Contact
Contact length, L c
Wid
th (W
)
ChannelContactGraphene nanoribbon
C
S
S
Channel length, L
Figure 1: Top view of GNRFET device structure with contact and channel design layout architecture.
0 50 100 150 2000
50
100
150
200
250
Technology process (nm)
Con
tact
size
, C (n
m)
Contact size
Process design kitLinear regression
(a)
0 50 100 150 2000
20
40
60
80
100
120
140
160
180
200
Technology process (nm)
Spac
er si
ze, S
(nm
)
Spacer size
Process design kitLinear regression
(b)
Figure 2: Interpolation of (a) contact and (b) spacer sizes.
Table 2: Values for the coefficients A to G.
Coefficient ValueA β3.5000 Γ 10β2
B 1.0737 Γ 10β3
C β2.7542 Γ 10β3
D 2.3754 Γ 10β3
E β6.3691 Γ 10β4
F β8.8009 Γ 10β1
G β3.5738 Γ 10β4
The coefficients π΄ to πΊ in Table 2 are empirical parame-ters used for curve fitting (2).
HSPICE utilizes (8) to simulate the drain and gate πΌ-πcharacteristic of GNRFET and MOSFET. The noniterativemodel allows cross-platform simulation, shorter executiontime, and reduced computational cost [26]. In GNRFET,when gate and drain voltages are applied, πSC is reduced byππΏ. This would result in a flow of electron in the channel
that increasesπSC byππ due to introduction of the additionalcharges [27]. In the πΌπ-ππ simulation of GNRFET, the πΌπ-ππequation can be written in ππ, ππ and ππ coefficients as givenby
πΌπ (ππ, ππ, ππ )
= πΊONππ΅π
π[log(1+exp(
π (πΈπΉ β πSC (ππ, ππ, ππ ))
ππ΅π))] . . .
β πΊONππ΅π
π
Γ [log(1+exp(π (πΈπΉβπSC (ππ, ππ, ππ )β ππ β ππ )
ππ΅π))] ,
(8)
where πΊON is the on-conductance.
4 Journal of Nanomaterials
0 0.2 0.4 0.6 0.8 10
5
10
15
20
25
30
GNRFETn-type MOSFETp-type MOSFET
Vd (V)
I d(π
A)
Figure 3: πΌπ-ππ characteristics n-type GNRFET, p-type, and n-typeMOSFET for various gate voltages starting from ππ = 1V at the topin 0.1 V decrement.
5. Device Simulation
The device performance of GNRFET and MOSFET arecompared by evaluating their respective πΌπ-ππ characteristicas shown in Figure 3. The output response of p-type and n-type MOSFETs is superimposed for comparison purposes.Also, the πΌπ-ππ characteristics of p-type and n-typeGNRFETsare symmetrical as in a CMOS and thus coincide with eachother. Figure 4 illustrated the πΌπ-ππ transfer characteristic ofn-type and p-type MOSFET and GNRFET. DIBL and SS arecalculated from the πΌπ-ππ curve and are given as
DIBL = ππππππ
,
SS =πππ
π (log10πΌπ).
(9)
The range of the DIBL measurement is taken between |ππ| =0.1V and |ππ| = 1V and the SS measurement is for the draincurrent curve at |ππ| = 0.1V. As deduced from Figure 3,GNRFET has a lower linear on-conductance compared toMOSFET. In addition, GNRFET achieves higher saturationcurrent values than those of MOSFET for most gate voltages.
As listed in Table 3, the DIBL of MOSFET is betterthan GNRFET. The subthreshold swing (SS) of both devicesis comparable. The πΌon/πΌoff ratio of GNRFET is two-ordermagnitude lower than that of MOSFET.This is due to a lowerlinear on-conductance limit of a ballistic GNRFET. The on-conductance limit, πΊON, with zero contact resistance is givenby
πΊON =2π2
β, (10)
Table 3: Device parameters and performance metrics of GNRFET,n-type, and p-type MOSFET.
Parameter GNRFET n-typeMOSFETp-type
MOSFETElectrical gate oxidethickness (nm) 2.0 1.0 1.6
Gate dielectric constantrelative to vacuum 25 25 25
Subthreshold swing(mV/decade) 70.1704 61.7527 70.7253
Drain-induced barrierlowering (mV/V) 40.7448 35.2515 36.6697
On/off ratio, (πΌon/πΌoff ) 3.42 Γ 104 1.25 Γ 106 6.9868 Γ 105
where π is the electronic charge and β is Planckβs constant.The simulation is carried out using a high gate dielectricconstant (high-π) with high thermal stability. In a practicalmicrofabrication, zirconium dioxide which has high-π valuesbetween 20 and 25 is considered [28].
Note that different values of oxide thickness are beingused to obtain almost symmetrical πΌ-π characteristics forboth p-type and n-type MOSFET, namely, in the linearregion. It is found that when all the transistors adopt equaloxide thickness, the maximum current at ππ = 1V and ππ =1V differs from one another. The output waveform will nothave uniform square wave anymore. The propagation delay,rise time, and fall time will be significantly affected. Thus,they are no longer suitable for logic application due to themismatch of the p-type and n-type πΌπ-ππ curves at the voltagetransfer characteristics.
6. Circuit Design
In this Section, circuit simulation is considered. As partof the circuit design process, parasitic capacitance, namely,load capacitance πΆπΏ is determined for an accurate circuitrepresentation. The top diagram in Figure 5 shows a typicalarrangement of two inverters in series with πΆπΏ. The compo-nents of πΆπΏ are gate-drain capacitance πΆgd1, πΆgd2, drain-bulkcapacitance πΆdb1, πΆdb2, and wire capacitance πΆπ as depictedin the bottom diagram of Figure 5. Note that the termwire capacitance is used interchangeably with interconnectcapacitance. Table 4 lists the local, intermediate, and globalcopper and GNRFET interconnect capacitances for 32 nm,22 nm, and 14 nm technology process. The finite elementmethod (FEM) charts the pathways in obtaining capacitancesas in [29]. The interconnects used in the simulation areconsidered to be in the intermediate layer [30] and vary from1 πm to 100 πm in length [31]. It is found that for 0.18 πmtechnology, average interconnect lengths are considered to be7 πmper fan-out [31].These interconnect specifications fromITRS 2005 are shown in Table 4.
Table 5 shows the extrapolated interconnect capacitancesfor the 90 nm, 65 nm, 45 nm, and 16 nm process technologies.The capacitance values of copper and metallic GNR areextrapolated from Figure 6 using a linear function based onthe intermediate capacitance in Table 4.
Journal of Nanomaterials 5
β1 β0.5 0 0.5 110β11
10β10
10β9
10β8
10β7
10β6
10β5
10β4
MOSFET
p-type n-type
Vd
= +/β 0.1 VVd
= +/β 1 V
Vg (V)
I d(π
A)
(a)
10β11
10β10
10β9
10β8
10β7
10β6
10β5
10β4
Vd
= +/β 0.1 VVd
= +/β 1 V
β1 β0.5 0 0.5 1
GNRFET
p-type n-type
Vg (V)I d
(πA
)
(b)
Figure 4: πΌπ-ππ transfer characteristic of n-type and p-type (a) MOSFET and symmetrical n-type and p-type (b) GNRFET FET for |ππ| =0.1V and |ππ| = 1V.
VCC
M1M1
M2
M3
M4
Cgd12
VCC
Cdb2
Cdb1
CW
Cgs3
Cgs4
CG3
CG4
CL
Vout
Vout
Vout2
Vout2
Vin
Vin
Figure 5: Two-cascaded inverter gate with parasitic capacitance.
Table 6 contains the relevant equations for the load andoutput capacitance for the logic gates.
7. Performance Analysis of Digital Circuit
HSPICE is used to simulate the logic operations of GNR-FET and MOSFET. The schematic diagram and input-output waveforms of GNRFET and MOSFET NOT, two-input NAND (NAND2), two-input NOR (NOR2), three-input NAND (NAND3), and three-input NOR (NOR3) gates
are delineated in Figures 7, 8, 9, 10, and 11, respectively. Allthe logic gates consist of 1 πm copper interconnects at theoutput terminals. In the simulation, the maximum fan-infor a gate is limited to 3. Correct logical operations areconfirmed from the simulation results as shown in theinput-output waveforms. Voltage spikes observed are foundto be negligible in the output waveform of MOSFET inFigures 7(b)β11(b). The circuit inductance possibly causesspikes that are possible to be compensated by incorporatingan on-chip decoupling capacitor at the output in parallel.Note that Figures 7βFigure 11 are important to calculate thepropagation delay which is computed between 50% of theinput rising to the 50% of the output rising. Together withthe average power consumption, the metric performance oflogic gates in termof EDP andPDP is obtained. PDP andEDPparameters are the figure of merit for logic devices. PDP andEDP are given by
PDP = πav Γ π‘π,
EDP = PDP Γ π‘π,(11)
whereπav is the average power and π‘π is the propagation delay.Table 7 lists the πav and π‘π for various logic gates as obtainedfrom the simulation. The PDP and EDP for GNRFET arean order of lower magnitude compared to MOSFET dueto smaller π‘π and its ultralow πav during logic operation asrevealed in Table 7. GNRFET power consumption is by atleast 1 order of magnitude lower than that of a MOSFET.
6 Journal of Nanomaterials
0 20 40 60 800
50
100
150
200
250
Technology process (nm)
Cop
per c
apac
itanc
e (p
F/m
)
Copper interconnect capacitance
ITRS 2005Interpolation
(a)
0 20 40 60 800
50
100
150
200
250
Technology process (nm)G
NRF
ET c
apac
itanc
e (p
F/m
)
GNRFET interconnect capacitance
ITRS 2005Interpolation
(b)
Figure 6: Extrapolation of interconnect capacitance for copper and GNR.
In Out
VDD
(a)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
VA
Inverter gate for GNRFET with 1πm interconnect
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
Time (s)
Time (s)0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
00.5
1
VA
Inverter gate for MOSFET with 1πm interconnect
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
Time (s)
Time (s)
Vou
t
Vou
t
Γ10β7
Γ10β7
Γ10β7
Γ10β7
(b)
Figure 7: (a) Schematic of NOT gate. (b) Input and output waveforms for GNRFET and MOSFET with 1 πm interconnect.
Journal of Nanomaterials 7
A B
A
B
Out
VDD
(a)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
Time (s)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
Time (s)
Time (s) Time (s)
Time (s) Time (s)
VA
VB
Vou
t
VA
VB
Vou
t
NAND2 gate for GNRFET with 1πm interconnect NAND2 gate for MOSFET with 1πm interconnect
Γ10β7
Γ10β7
Γ10β7
Γ10β7
Γ10β7
Γ10β7
(b)
Figure 8: (a) Schematic of NAND2 gate. (b) Input and output waveforms for GNRFET and (b) MOSFET with 1 πm interconnect.
Table 4: ITRS 2005 based simulation parameters (adapted from[22]).
Technology process (nm) 32 22 14Local and intermediate
WidthW (nm) 32 22 14ILD thickness π‘ox (nm) 54.40 39.60 25.20πΆcu (pF/m) 144.93 131.01 111.83πΆgnrfet (pF/m) 130.15 117.70 100.51
GlobalWidthW (nm) 48 32 21ILD thickness π‘ox (nm) 110.40 76.80 52.50πΆcu (pF/m) 179.78 163.30 139.30πΆgnrfet (pF/m) 163.81 148.90 126.78
Figure 12 depicts the layout for GNRFET NOR2schematic shown in Figure 9(a). In the top-gated design, the
Table 5: Interconnect capacitances for 16, 45, 65, and 90 nm nodes.
Capacitance Technology process (nm)90 65 45 16
πΆcu (pF/m) 252.32 206.60 170.03 116.99πΆgnr (pF/m) 226.87 185.70 152.76 105.01
GNR is placed under the metal gate and thus hidden fromthe view. The ππ is supplied to the device through terminalsA and B. The vertical-interconnect-access (via) as labeled inFigure 12 allows a conductive connection between differentlayers. To realize the number of p-type and n-type transistorsas given in Figure 9(a), three and four electrode contacts,respectively, are implemented in the layout. While the seriesconfiguration of the p-type transistors requires only threeelectrode contacts, and four electrode contacts are neededfor the n-type transistors connected in parallel.
8 Journal of Nanomaterials
A
B
A B
Out
VDD
(a)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
Time (s)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
Time (s)
Time (s) Time (s)
Time (s) Time (s)
VA
VB
Vou
t
VA
VB
Vou
t
NOR2 gate for GNRFET with 1πm interconnect NOR2 gate for MOSFET with 1πm interconnect
Γ10β7
Γ10β7 Γ10β7
Γ10β7
Γ10β7
Γ10β7
(b)
Figure 9: (a) Schematic of NOR2 gate. (b) Input and output waveforms for GNRFET and (b) MOSFET with 1 πm interconnect.
Table 6: Load and output capacitance for logic gates NOT, two-input NAND, two-input NOR, three-input NAND, and three-input NOR.
Gate logic CapacitanceNOT πΆπΏ = πΆgd1 + πΆgd2 + πΆdb1 + πΆdb2 + πΆπTwo-input NAND πΆ1 = πΆdb1 + πΆsb2 + πΆgd1 + πΆgs2Two-input NOR πΆπΏ = πΆdb2 + πΆdb3 + πΆdb4 + πΆgd2 + πΆgd3 + πΆgd4 + πΆπThree-input NAND πΆ1 = πΆdb1 + πΆsb2 + πΆgd1 + πΆgs2Three-input NOR πΆ
2= πΆdb2 + πΆsb3 + πΆgd2 + πΆgs3
πΆπΏ = πΆdb3 + πΆdb4 + πΆdb5 + πΆdb6 + πΆgd3 + πΆgd4 + πΆgd5 + πΆgd6 + πΆπ
The Fermi velocity in a GNRFET is distinctly higherthan that in a heavily dopedMOSFET. Obviously, degeneratestatistics is applicable in heavily doped channels.The intrinsicvelocity for a nondegenerate low-doping level is limited tothe thermal velocity which is lower than the Fermi velocityin heavily doped semiconductors. The device modeling ofGNR adopts similar modeling framework in [17] where we
havemodified the density of states and quantum conductancelimit of a ballistic SWCNT to GNR. The maximum draincurrent for a monolayer GNRFET is found to be at 19 πA. ForCNTFET, the maximum drain current is at 46 πA. Neverthe-less, both low dimensional carbon devices outperform siliconMOSFET in term of power-delay-product (PDP) and energy-delay-product (EDP) by at least one order of magnitude.
Journal of Nanomaterials 9
A B
A
B
Out
C
C
VDD
(a)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
Time (s)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
Time (s)
Time (s) Time (s)
Time (s) Time (s)
Time (s) Time (s)
VA
VB
VC
Vou
t
VA
VB
VC
Vou
t
NAND3 gate for GNRFET with 1πm interconnect NAND3 gate for MOSFET with 1πm interconnect
Γ10β7
Γ10β7
Γ10β7
Γ10β7
Γ10β7
Γ10β7
Γ10β7
Γ10β7
(b)
Figure 10: (a) Schematic of NAND3 gate. (b) Input and output waveforms for GNRFET and (b) MOSFET with 1 πm interconnect.
Table 7: Propagation delay and average power consumption of GNRFET and MOSFET with L = 16 nm and 1 πm interconnect for variouslogic gates.
Logic gates Propagation delay, π‘π (ps) Average power, πav (nJ/s)GNRFET MOSFET GNRFET MOSFET
Inverter 4.825 14.02 2.90 96.11Two-input NAND 7.059 44.90 3.13 124.04Three-input NAND 9.555 58.82 3.24 270.18Two-input NOR 7.059 44.95 3.07 122.12Three-input NOR 9.589 58.19 3.24 286.58
10 Journal of Nanomaterials
A
B
A B
Out
C
C
VDD
(a)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
Time (s)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60
0.51
Time (s)
Time (s) Time (s)
Time (s) Time (s)
Time (s) Time (s)
NOR3 gate for GNRFET with 1πm interconnect NOR3 gate for MOSFET with 1πm interconnectV
AV
BV
CV
out
VA
VB
VC
Vou
t
Γ10β7
Γ10β7
Γ10β7
Γ10β7
Γ10β7
Γ10β7
Γ10β7
Γ10β7
(b)
Figure 11: (a) Schematic of NOR3 gate. (b) Input and output waveforms for GNRFET and (b) MOSFET with 1 πm interconnect.
Figure 13 depicts the GNRFET PDP and EDP, respec-tively, for 0β100 πm copper interconnects in length for var-ious logic gates. Figure 14 shows the MOSFET PDP and EDP,respectively, for 0β100πm copper interconnect in length forvarious logic gates. The logic gates with high fan-in exhibitincreased EDP andPDP as exhibited by these plots.The cutofffrequency at which the current gain is 1 is used to describethe high-frequency performance of a transistor. The currentunity gain cutoff frequency of the intrinsic transistor [32, 33]with interconnect capacitance is given by
ππ =1
2π
ππ
πΆπ + CπΏ + πΆsub, (12)
where πΆπ is the gate capacitance, πΆπΏ is the load capacitance,and πΆsub is the substrate capacitance. Devices with thickersubstrate insulator (for instances, 500 nm) and smaller con-tact area have higher unity cutoff frequency.Theunity currentgain cutoff frequency for GNRFET circuit model is depictedin Figure 15. The model uses a copper interconnect of the16 nm, 45 nm, 65 nm, 9 and 0 nm nodes technology. Thesimulation shows that a 16 nm GNRFET can deliver a unitycutoff frequency of 400GHz. The interconnect length variesfrom 0.01πm to 100πm. It is found that cutoff frequencyis inversely proportional to interconnect length. When theinterconnects are longer than 10 πm, the frequency remainsthe same regardless of the technology nodes. Therefore, it
Journal of Nanomaterials 11
Metal
Gate contact
Electrode contact
Output
Via
p-type FET
n-type FET
Figure 12: Proposed layout of GNRFET NOR2 gate with metalcontacts and interconnects.
is essential to utilize interconnects as short as possible totap the high-frequency capability of the CNTFETs [17] andGNRFETs. Our finding is consistent with the state-of-the-artgraphene transistors that have been shown to reach operatingfrequencies up to 300GHz experimentally [34].
8. Conclusions
Complementary CMOS based on π-type and π-type MOS-FETs has been at the center stage in industrial environmentsbecause of low power consumption. A CMOS circuit drawspower from the source only when an inverter is switchingfrom low to high or vice versa. A CMOS inverter is abuilding block for other gates to build a complete ultralarge-scale-integrated (ULSI) ensemble. After the 2010 Nobel Prizeawarded to graphene, graphene allotropes have overwhelmedthe center stage to capture the advantage ofMore thanMooreβsEra. In fact, Arora and Bhattacharyya [35] show that CNTband structure can be drawn from that of graphene nanolayerwith rollover in various chirality directions. GNR [36] offerssimilar endless opportunities. Considering these noteworthydevelopments, we believe that graphene allotropes offerdistinct advantage over and above the CMOS architecturefor a variety of applications in creating sensors, actuators,and transistors for implementation in the ULSI. As grapheneallotropes bring to focus the advanced applications, weconsider GNR as an example to demonstrate its superiorityover the CMOS. Primary reason why graphene is superiorto silicon is its intrinsic velocity. The drift in graphene islimited to the Fermi velocity VπΉ β 10
6m/s that is 10 times thanthat of a silicon (Vπ β 10
5m/s). Saturation velocity limited tothe intrinsic velocity Vπ determines the high-frequency cutoffof a ULSI circuit. That is the reason that graphene-basedelectronics will offer unique advantage in high-frequencycircuit design. As current saturates, the power in a ULSIcircuit is governed by π = ππΌsat and hence becomes a linearfunction of voltage, in direct contrast to square law dictatedby Ohmβs law. The power consumption will be much lowerin a graphene circuit affording the opportunity to lower thescale of the voltage source. Power-frequency product is a
figure of merit in ULSI applications.The paper shows distinctadvantages of graphene-based integration in ULSI circuitsin designing various Boolean gates. The comparative studystretches the landscape ofMore than Moore era as traditionalscaling reaches its limit. As demonstrated by Greenberg anddel Alamo [37], interconnect degrades the device behavior.That iswhy it is important to include interconnects in the totalpackage of these studies. The rise in the resistance in scaled-down channels also affects the voltage divider and currentdivider principles, normally based on Ohmβs law. Wheninterconnects are considered in series with the channel, theresistance surges for a smaller length resistor, creating theimportance of comprehensive study [38]. Similarly, whenparasitic channels are considered in parallel with the con-ducting channel, the resistance can be higher than what ispredicted fromOhmβs law.This rise in resistance can increasethe RC time constants as demonstrated in [38, 39]. GNRFETwith proper architecture can extend the domain ofMore thanMoore era in meeting the requirements of the future. Short-channel effects that restrict the silicon technology to reachits full potential are controllable in GNRFET architecture.GNRFET has shown comparable device performance against16 nm CMOS node. In terms of circuit performance inlogic design, the PDP and EPD of GNRFET are distinctlybetter. The modern adage is βsilicon comes from geology,but carbon comes from biology.β This transformation fromsilicon to carbon-based graphene will usher new era forcircuit design based on carbon electronics that is expected tobe compatible with bioelements. ULSI designers will greatlybenefit from this comparative study as they change theirmode of thinking from CMOS to new graphene-based ULSI.We are also expecting that parasitic elements that inhibit thespeed of ULSI circuits will pose less of a problem in futurearchitectures based on our findings. The all-encompassinglandscape covered in this paper will find broader applicationsbenefitting not only the research labs in their characterizationandperformance evaluation, but also in giving newdirectionsto the industry in product development that will benefitglobal community.
Conflict of Interests
The authors declare that there is no conflict of interestsregarding the publication of this paper.
Acknowledgments
The authors would like to acknowledge the financialsupport from UTM GUP Research Grant (Vote nos.:Q.J130000.2523.04H32 and Q.J130000.2623.09J21) andFundamental Research Grant Scheme (FRGS) (Votenos.: R.J130000.7823.4F247, R.J130000.7823.4F273, andR.J130000.7823.4F314) of the Ministry of Higher Education(MOHE), Malaysia. Weng Soon Wong thanks YayasanSime Darby (YSD) for the scholarship given for his study atthe Universiti Teknologi Malaysia (UTM). Vijay K. Aroraappreciates the Distinguished Visiting Professorship of theUTM. UTM Research Management Centre (RMC) provided
12 Journal of Nanomaterials
CMOS NAND2
NAND3NOR2 NOR3
0
50
1000
0.5
1
1.5
Logic gates
PDP of GNRFETPo
wer
-del
ay p
rodu
ct (J
)
Interconnect length (πm)
Γ10β16
(a)
CMOS NAND2
NAND3NOR2 NOR3
0
50
1000
0.5
1
Logic gates
EDP of GNRFET
Ener
gy-d
elay
pro
duct
(J.s)
Interconnect length (πm)
Γ10β25
(b)
Figure 13: (a) PDP and (b) EDP of GNRFET logic gates for copper interconnect length from 0 to 100 πm.
CMOS NAND2NAND3
NOR2 NOR3
0
50
1000
0.5
1
1.5
Logic gat
es
PDP of MOSFET
Pow
er-d
elay
pro
duct
(J)
Interconnect length (πm)
Γ10β15
(a)
CMOS NAND2
NAND3NOR2
NOR3
0
50
1000
0.5
1
1.5
2
2.5
Logic gates
EDP of MOSFET
Ener
gy-d
elay
pro
duct
(J.s)
Interconnect length (πm)
Γ10β24
(b)
Figure 14: (a) PDP and (b) EDP of MOSFET logic gates for copper interconnect length from 0 to 100 πm.
10β2 10β1 100 101 1020
50
100
150
200
250
300
350
400
Cut
off fr
eque
ncy
(GH
z)
16 nm node45 nm node
65 nm node90 nm node
Length of interconnect (πm)
Figure 15: Unity cutoff frequency for GNRFET based on 16 nm,45 nm, 65 nm, and 90 nm process technology.
excellent support conduciveness to the research environmentneeded to complete project of this magnitude with personnelof far-reaching background.
References
[1] C. A. MacK, βFifty years of Mooreβs law,β IEEE Transactions onSemiconductor Manufacturing, vol. 24, no. 2, pp. 202β207, 2011.
[2] T. Saxena, D. C. Y. Chek, M. L. P. Tan, and V. K. Arora,βMicrocircuit modeling and simulation beyond Ohmβs law,βIEEE Transactions on Education, vol. 54, no. 1, pp. 34β40, 2011.
[3] V. K. Arora, βQuantum transport in nanowires andnanographene,β in Proceedings of the 28th InternationalConference on Microelectronics (MIEL β12), Nis, Serbia, 2012.
[4] V. K. Arora, D. C. Y. Chek, M. L. P. Tan, and A. M. Hashim,βTransition of equilibrium stochastic to unidirectional velocityvectors in a nanowire subjected to a towering electric field,βJournal of Applied Physics, vol. 108, no. 11, Article ID 114314, 2010.
[5] R. Vidhi, M. L. P. Tan, T. Saxena, A. M. Hashim, and V. K.Arora, βThe drift response to a high-electric-field in carbon
Journal of Nanomaterials 13
nanotubes,β Current Nanoscience, vol. 6, no. 5, pp. 492β495,2010.
[6] V. K. Arora, M. L. P. Tan, and C. Gupta, βHigh-field transportin a graphene nanolayer,β Journal of Applied Physics, vol. 112,Article ID 114330, 2012.
[7] M. L. P. Tan, βLong channel carbon nanotube as an alternativeto nanoscale silicon channels in scaled MOSFETs,β Journal ofNanomaterials, vol. 2013, Article ID 8312521, 5 pages, 2013.
[8] A. Pourasl, M. T. Ahmadi, M. Rahmani et al., βAnalyticalmodeling of glucose biosensors based on carbon nanotubes,βNanoscale Research Letters, vol. 9, article 33, 2014.
[9] V. K. Arora, βTheory of scattering-limited and ballistic mobilityand saturation velocity in low-dimensional nanostructures,βCurrent Nanoscience, vol. 5, no. 2, pp. 227β231, 2009.
[10] H. Xu, βThe logical choice for electronics?β Nature Materials,vol. 4, no. 9, pp. 649β650, 2005.
[11] A. Raychowdhury and K. Roy, βCarbon nanotube electronics:design of high-performance and low-power digital circuits,βIEEE Transactions on Circuits and Systems I, vol. 54, no. 11, pp.2391β2401, 2007.
[12] M. L. P. Tan and G. A. J. Amaratunga, βPerformance predictionof graphene nanoribbon and carbon nanotube transistors,β inProceedings of the International Conference on Enabling Scienceand Nanotechnology (EsciNano β10), vol. 1341 of AIP ConferenceProceedings, pp. 365β369, December 2010.
[13] L. Liao, J. Bai, R. Cheng et al., βTop-gated graphene nanoribbontransistors with ultrathin high-π dielectrics,β Nano Letters, vol.10, no. 5, pp. 1917β1921, 2010.
[14] G. S. Kliros, βGate capacitance modeling and width-dependentperformance of graphene nanoribbon transistors,β Microelec-tronic Engineering, vol. 112, pp. 220β226, 2013.
[15] W. Wang, X. Yang, N. Li, L. Zhang, T. Zhang, and G. Yue,βNumerical study on the performance metrics of lightly dopeddrain and source graphene nanoribbon field effect transistorswith double-material-gate,β Superlattices and Microstructures,vol. 64, pp. 227β236, 2013.
[16] D. C. Y. Chek, M. L. P. Tan, M. T. Ahmadi, R. Ismail, andV. K. Arora, βAnalytical modeling of high performance single-walled carbon nanotube field-effect-transistor,βMicroelectronicsJournal, vol. 41, no. 9, pp. 579β584, 2010.
[17] M. L. P. Tan, G. Lentaris, and G. A. Amaratunga, βDevice andcircuit-level performance of carbon nanotube field-effect tran-sistor with benchmarking against a nano-MOSFET,β NanoscaleResearch Letters, vol. 7, article 467, 2012.
[18] Z. Johari, F. K. A. Hamid, M. L. P. Tan, M. T. Ahmadi,F. K. C. Harun, and R. Ismail, βGraphene nanoribbon fieldeffect transistor logic gates performance projection,β Journal ofComputational and Theoretical Nanoscience, vol. 10, pp. 1164β1170, 2013.
[19] N. Bahador,M. L. P. Tan,M.T.Ahmadi, andR. Ismail, βAunifieddrain-current model of silicon nanowire field-effect transistor(SiNWFET) for performance metric evaluation,β Science ofAdvanced Materials, vol. 6, pp. 354β360, 2014.
[20] B. J. Sheu, D. L. Scharfetter, P.-K. Ko, and M.-C. Jeng, βBSIM:Berkeley short-channel IGFET model for MOS transistors,βIEEE Journal of Solid-State Circuits, vol. 22, no. 4, pp. 558β566,1987.
[21] X. Xuemei, D. Mohan, M. H. Tanvir, L. D. Darsen, M. Yang, andH. Jin, BSIM4 Homepage, 2013, http://www-device.eecs.berke-ley.edu/bsim/?page=BSIM4 LR.
[22] H. Li, W.-Y. Yin, K. Banerjee, and J.-F. Mao, βCircuit modelingand performance analysis of multi-walled carbon nanotubeinterconnects,β IEEE Transactions on Electron Devices, vol. 55,no. 6, pp. 1328β1337, 2008.
[23] S. Datta, Quantum Transport: Atom to Transistor, CambridgeUniversity Press, 2005.
[24] M. L. P. Tan,Device and circuit-level models for carbon nanotubeand graphene nanoribbon transistors [Ph.D. thesis], Departmentof Engineering, University of Cambridge, Cambridge, UK, 2011.
[25] T. J. Kazmierski, D. Zhou, and B. M. Al-Hashimi, βA fast,numerical circuit-level model of carbon nanotube transistor,β inProceedings of the IEEE International Symposium on NanoscaleArchitectures (NANOARCH β07), pp. 33β37,NewYork,NY,USA,October 2007.
[26] A. Balijepalli, S. Sinha, and Y. Cao, βCompact modeling ofcarbonnanotube transistor for early stage process-design explo-ration,β in Proceedings of the International Symposium on LowPower Electronics and Design (ISLPED β07), pp. 2β7, Portland,Ore, USA, August 2007.
[27] A. Rahman, J. Guo, S. Datta, and M. S. Lundstrom, βTheoryof ballistic nanotransistors,β IEEE Transactions on ElectronDevices, vol. 50, no. 9, pp. 1853β1864, 2003.
[28] T. H. Ng, B. H. Koh, W. K. Chim et al., βZirconium dioxide as agate dielectric in metal-insulator-silicon structures and currenttransport mechanisms,β in Proceedings of the IEEE InternationalConference on Semiconductor Electronics (ICSE β02), pp. 130β134,2002.
[29] J. Xu, H. Li,W.-Y. Yin, J.Mao, and L.-W. Li, βCapacitance extrac-tion of three-dimensional interconnects using element-by-element finite elementmethod (EBE-FEM) and preconditionedconjugate gradient (PCG) technique,β IEICE Transactions onElectronics, vol. E90-C, no. 1, pp. 179β187, 2007.
[30] βProcess Integration, Devices, & Structures Process Inte-gration,β in International Technology Roadmap for Semicon-ductors (ITRS), 2005, http://www.itrs.net/links/2005itrs/Inter-connect2005.pdf.
[31] M. Vujkovic, D. Wadkins, and C. Sechen, βEfficient post-layout power-delay curve generation,β in Integrated Circuit andSystem Design. Power and Timing ModelIng, Optimization andSimulation, V. Paliouras, J. Vounckx, and D. Verkest, Eds., vol.3728, pp. 393β403, Springer, Berlin, Germany, 2005.
[32] J. Guo, S. Hasan, A. Javey, G. Bosman, and M. Lundstrom,βAssessment of high-frequency performance potential of car-bon nanotube transistors,β IEEE Transactions on Nanotechnol-ogy, vol. 4, no. 6, pp. 715β721, 2005.
[33] Y. Yoon, Y. Ouyang, and J. Guo, βEffect of phonon scattering onintrinsic delay and cutoff frequency of carbon nanotube FETs,βIEEE Transactions on Electron Devices, vol. 53, no. 10, pp. 2467β2470, 2006.
[34] Y. Wu, K. A. Jenkins, A. Valdes-Garcia et al., βState-of-the-artgraphene high-frequency electronics,β Nano Letters, vol. 12, pp.3062β3067, 2012.
[35] V. K. Arora and A. Bhattacharyya, βCohesive band structureof carbon nanotubes for applications in quantum transport,βNanoscale, vol. 5, pp. 10927β10935, 2013.
[36] V. K. Arora and A. Bhattacharyya, βEquilibrium and nonequi-librium carrier statistics in carbon nano-allotropes,β in Physicsof Semiconductor Devices, V. K. Jain and A. Verma, Eds., pp. 511β516, Springer, 2014.
[37] D. R. Greenberg and J. A. del Alamo, βVelocity saturation inthe extrinsic device: a fundamental limit in HFETβs,β IEEE
14 Journal of Nanomaterials
Transactions on Electron Devices, vol. 41, no. 8, pp. 1334β1339,1994.
[38] M. L. P. Tan, T. Saxena, and V. K. Arora, βResistance blow-upeffect in micro-circuit engineering,β Solid-State Electronics, vol.54, no. 12, pp. 1617β1624, 2010.
[39] M. L. P. Tan, I. Saad, R. Ismail, and V. K. Arora, βEnhancementof nano-RC switching delay due to the resistance blow-up inInGaAs,β Nano, vol. 2, pp. 233β237, 2007.
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