Reconfigurable ComputingBrittany RansbottomBenjamin Wheeler

What is Reconfigurable Computing?

A computer architecture style which tries to find a happy medium of general purpose processors and ASICs through the use of the flexibility of software, and the speed of hardware.

Reconfigurable Computing

von Neumann vs. Reconfigurable

Fixed resourcesThe architecture is designed prior to use as a processor

Execution in SW

Variable resourcesWhile the

architecture is designed prior to use, it can be adjusted or reconfigured to use different resources

Execution in HW

Spatial vs. Temporal

Hardware SoftwareSoftware

The Reconfigurable Computing Paradox

• Migration from software to configwareo speed-up factors and

electricity consumption reduction of about four orders of magnitude

o Clock frequency and other specifications of FPGAs are behind microprocessors by about four orders of magnitude

Current State

No designs merge GPP and ASIC enough to be marketable

Too specialized (a glorified asic), or priced too high to benefit replacing GPPs

Coarse-Grained doesn't have SW support necessary

What is an FPGA?

Reprogrammable Hardware

Generally configured in VHDL or Verilog

Can execute processes spatially as opposed to temporally

The FPGA Coprocessor Option

+Reprogrammable Logic

-Requires pre-existing HW design

-Needs to be specific processing, or have an intensive controller/compiler

What is Coarse-grained computingFunctional units (add, subtraction,

multiplication - word-level operations) interconnected in a mesh style

Coarse-Grained

+Short Reconfiguration Times

+Low Delay Characteristics

+Low Power consumption

-No Gate-level reconfigurability

-Large stress for the scheduling level of a compiler (sparse connectivity, distributed register files)

Coarse-Grained Architectures

• Two main classeso Linear Array

Very efficient for linearly pipelineable applicationsStruggles to support block-based applicationsExamples: RaPiD, PipeRench, RCP

o Mesh-basedMuch more efficient for 2D applicationsExamples: KressArray, MATRIX, MorphoSys, ADRES

FPGA Advances

FPGAs now support dynamic partial reconfiguration

Allows for sub-units, rather than reconfiguringthe entire FPGA

These units can be loaded with different functions

Image Processing Using Partially Reconfigurable Blocks for co-processing

Algorithm Image Size MicroBlaze Time (s)

SFU Time (s)(6 SFUs)

Speedup

Sobel Edge

Detection

Smile120

120x120

23.057 1.907 12.1

Kirsch Edge

Detection

Smile120

120x120

23.111 1.864 12.4

Prewitt Edge

Detection

Smile120

120x120

23.051 1.908 12.1

FPGA Partial Reconfiguration

+Lower-level Hardware design and implementationCloser to a GPP

+Significant Speed-upCloser to an ASIC

-Deeper knowledge of system needs on the fly

Future Potential

Coarse-grained and FPGA designs are both viable

Both designs require very good compilers

Compilation of code and determination of design intent prior to execution appears to be the biggest delay moving forward

Conclusion

Reconfigurable Computing has a long way to go, but is definitely a viable option for the future.

Questions?