Recall an earlier slide describing two types of state diagrams.

Recall an earlier slide describing two types of state diagrams. Mealy state machine (Mealy model) – the output depends on the present state and the inputs applied.Moore state machine (Moore model) – the output only depends on the present state.

Mealy Model • Transition from one state to another

depends on the Input, X• Output, Y, is specified with the transition• Output, Y, depends on both the Present

State and the Input, X

Moore Model• Transition from one state to another

depends on the Input, X• Output, Y, is specified with the

Present State• Output, Y, depends only on the

Present State

We will primarily use Mealy

models

1Chapter 5B EGR 270 – Fundamentals of Computer EngineeringReading Assignment: - Chapter 5 in Logic and Computer Design Fundamentals, 4th Edition by Mano

Example: Both a Mealy Model and a Moore Model are used below to specify state machines that will detect the occurrence of two 1’s in a row.

• Two states (one flip-flop)• Output of 1 indicates that two inputs of 1

occurred in a row.• Output is not associated with a state, but

with the transition.

• Three states (two flip-flops)• Output of 1 indicates that two inputs of

1 occurred in a row.• Output is associated with state C.

State A: Zero 1’s receivedState B: One 1 received

State A: Zero 1’s receivedState B: One 1 receivedState C: Two 1’s received

Mealy Model: Moore Model:

2Chapter 5B EGR 270 – Fundamentals of Computer Engineering

Comparison of Mealy models and Moore models:

Mealy Model Moore Model

Output depends on both the Present State and the Inputs

Output depends only on the Present State

Specify output in transition Specify output in Present State

Generally requires fewer states Generally requires more states

Output may change immediately when input changes, so may change in the same clock

Output does not respond immediately to input change, but is synchronized with the

clockReacts faster to inputs Safer

Most of our textbook examples and class examples will use Mealy models

Sequence Detector: An example of a circuit whose output sequence is critical and the numeric value of the states is unimportant is a “sequence detector”. Such a circuit might be used to detect a certain bit pattern (such as in synchronizing two signals) or for a digital lock – where the lock is unlocked when a correct combination (sequence) is entered.

Chapter 5B EGR 270 – Fundamentals of Computer Engineering

Sequence DetectorInput, X Output, Y

detected sequenceInput 1

detectednot sequenceInput 0 Y

Example: Detect the sequence 101, including overlapping sequences. Define the output, Y, as follows:

Fill out the values for Y in the table below:

X 0 0 1 0 1 1 0 0 1 0 1 0 1 0 0 1Y

Example: Design a sequence detector to detect the sequence 1010. The sequence detector should also detect overlapping sequences. The circuit should output a binary 1 when a valid sequence is detected. Use a Moore model.

Test the state diagram with the input sequence 0101011001010100

State A

Input 0 1 0 1 0 1 1 0 0 1 0 1 0 1 0 0

Output

One strategy is to use 5 states:A - 0 correct values in sequenceB - 1 correct value in sequenceC - 2 correct values in sequenceD - 3 correct values in sequenceE - 4 correct values in sequence

Example: Repeat the previous example using a Mealy model. Note that only 4 states are required.

Test the state diagram with the input sequence 0101011001010100Is the output identical to the output from the previous example?

State A

Input 0 1 0 1 0 1 1 0 0 1 0 1 0 1 0 0

Output

One strategy is to use 4 states:A - 0 correct values in sequenceB - 1 correct value in sequenceC - 2 correct values in sequenceD - 3 correct values in sequence

Example: (continued) • How many flip-flops are required using the Moore model?• How many flip-flops are required using the Mealy model?• Complete the excitation table for the Mealy model circuit.

Example: (continued) Draw the logic diagram. Clearly label the input sequence, x, and the output sequence, y.

Example: Serial 2’s Complementer CircuitDesign a one input, one output serial 2’s complementer using a Mealy Model. The circuit accepts a string of bits from the input and generates the 2’s complement at the output. The circuit can be reset asynchronously to start and stop the operation. Implement the circuit using JK flip-flop(s).

Design: Recall that one method for finding a 2’s complement is to start with the LSB and proceed until the first 1 is encountered and then take the 1’s complement of all bits.

Serial 2’s Complementer

InputSequence, x

2’s complementof Input Sequence, y

1 0 0 1 1 0 00 1 1 0 1 0 0

complement

Input, x:

Output, y:

State A(output = input)

State B(output = 1’s complement of input)

Example: (continued)• Draw the state diagram using states A and B as defined on the previous slide

Example: (continued)• How many flip-flops are needed for 2 states?• Fill out the excitation table.

• Use K-maps to find expressions for J, K, and y

Input/ Present State

Next State

Flip-flop inputs Output

x Q Q J K y

Example: (continued)• Draw the logic diagram

Recall that three methods for designing sequential circuits will be covered:1) Excitation table method (already covered)2) State equation method3) “One-Hot” method

Designing Sequential Circuits using State EquationsBefore the state equation method is covered, two related topics must be covered:• state equations• flip-flop characteristic equations

State EquationsA state equation is an equation for the next state of a sequential logic circuit. It has the form:

Q(t + 1) = (Boolean expression involving present states and inputs) The state equations are simply formed using the “Next State” shown in the state table.

Example: Find the state equations for the state diagram shown below.

Flip-flop characteristic equationsFlip-flop behavior has been expressed so far using truth tables or excitation tables. The next state (output) of a flip-flop can also be described algebraically using a flip-flop state equation or flip-flop characteristic equation.

Example: Develop the flip-flop characteristic equation for a JK flip-flop.

Example: Develop flip-flop characteristic equations for SR, D, and T flip-flops.

Designing Sequential Circuits using State Equations – Procedure1. Form the state table.2. Develop the state equations from the state table.3. Determine the type of flip-flop to be used.4. Manipulate the state equation into the form of the characteristic equation

for each flip-flop. This will yield the flip-flop input expressions.

Notes:• It is easiest to design by state equations using D flip-flops.• Many programmable devices only support D flip-flop designs, so state

equations are very useful.• JK flip-flop designs will yield the simplest circuits in general.• Designing circuits by the excitation table method and by the state equation

method should yield the same results.

Example: Design a modulo-7 counter by the state equation method using D flip-flops

a) Create the state table

Present State Next State

A B C A(t+1) B(t+1) C(t+1)

Example: (continued)

b) Form the state equations

00 01 11 10

c) Determine the D flip-flop inputs (trivial!)

d) Draw the logic diagram using D flip-flops

Example: Repeat the last example using JK flip-flops.

a) Create the state table – same as beforeb) Form the state equations – same as beforec) Determine the JK flip-flop inputs (much harder than with D flip-flops)

State Equation A(t+1)

7A Theorem - BCA C BA 1)A(t

BCA BC BA 1)A(t

BCA ABC BA 1)A(t

AABC BA 1)A(t

BC BA 1)A(t So

)Aor A havemust each term (i.e.,A KA AJA 1)A(t

or QK QJ 1)Q(t

:flop-flipJK afor equation char. theof form in thePut BC BA 1)A(t

So JA = BCCB KA

C B KA

C B KA So

Example: (continued) - Repeat for the next two state equations

State Equation B(t+1)

State Equation C(t+1)

d) Draw the logic diagram using JK flip-flops

Three methods for designing synchronous sequential circuits:1) Excitation table method (already covered)2) State equation method (already covered)3) “One-Hot” method

“One-Hot” Method for designing synchronous sequential circuitsThe “one-hot” method is based on the idea that N flip-flops will be used to

represent N states and that at any given time only one of the states is “hot” or HIGH – the current state.

Example: A state diagram with 4 states would require 4 flip-flops and the outputs would be as follows:

Other connections and circuitry

State A is “hot”

Other connections and circuitry State B is

“hot”

(Similar diagrams for states C and D are not shown.)

“One-Hot” Method - Advantage The design process is simple for the “one-hot” method. The connections for D flip-flop designs can be seen easily from an ASM (Algorithmic State Machine) Chart, which is similar to a flowchart. Also note that this method can allow for a simple way to describe sequential circuits in VHDL.Algorithmic State Machine (ASM) Chart symbolsASM Charts are covered in more detail in Chapter 8 of the text. For now, we will just introduce two ASM chart symbols (elements).

State 0

X = 1?YN

Exit 1Exit 0

State box Decision box

“One-Hot” Method - DisadvantageThe “one-hot method requires a potentially large number of flip-flops. Since the states are not encoded as with other methods (i.e., one flip-flop is required for each state), designs may require a large number of flip-flops. Examples are provided below to illustrate this problem.

Sequential Circuit

# flip-flops using encoded states (state equations or excitation table method)

# flip-flops = log2(# states)

# flip-flops using the “one-hot” method

# flip-flops = # states3-bit (mod-8) counter

8-bit counter 8 256Circuit with 20 states

Note: When implementing sequential circuits using Aldec Active-HDL , the software gives the user a choice of implementing a “one-hot” design or using encoded states (the default) . Using encoded states saves many flip-flops.

Example: Use the “one-hot” method to design a mod-5 counter. Note that each state box essentially acts like a D flip-flop where the entry to the box is D and the exit from the box is Q.

State diagram

State 0

State 1

State 2

State 3

State 4

ASM Chart

So Q0(t+1) = D0 = Q4

So Q1(t+1) = D1 = Q0

So Q2(t+1) = D2 = Q1

So Q3(t+1) = D3 = Q2

So Q4(t+1) = D4 = Q3

State Equations

Example (mod-5 counter continued):

Q0(t+1) = D0 = Q4Q1(t+1) = D1 = Q0Q2(t+1) = D2 = Q1Q3(t+1) = D3 = Q2Q4(t+1) = D4 = Q3

Logic Diagram:

Recall that the outputs above are not encoded. An encoder can be used to create encoded outputs if they are needed (for example, to send the outputs to a BCD-to-7 segment decoder). This is illustrated on the following slide.

State Equations:

30Chapter 5B EGR 270 – Fundamentals of Computer EngineeringExample (mod-5 counter continued):

Logic Diagram with encoder added

01234567

(MSB) ABC

8 x 3Encoder

BCD-to7-segment decoder

D (LSB)

Exercise: Add binary values to the logic diagram if the counter is in state 3

Example: Use the “one-hot” method to design a mod-5 counter UP/DOWN.Let x be an input control where if:• x = 0 the counter counts down• x = 1 the counter counts up

State diagram

ASM Chart:

State 0

State 1

x = 0 or 1?10

State 2

x = 0 or 1?10

State 3

x = 0 or 1?10

State 4

x = 0 or 1?10

Q0(t+1) = D0 =

Q1(t+1) = D1 =

Q2(t+1) = D2 =

Q3(t+1) = D3 =

Q4(t+1) = D4 =

• Label D and Q next to each state box • Find the state equations

31Chapter 5B EGR 270

Example (mod-5 UP/DOWN counter continued) : Draw the logic diagram

Recall an earlier slide describing two types of state diagrams.

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