Post on 21-Feb-2018
7/24/2019 r05420402-Digital Design Through Verilog (1)
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SET-1R05Code.No: R05420402
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.TECH II SEMREGULAR/SUPPLEMENTARY EXAMINATIONS MAY - 2010
DIGITAL DESIGN THROUGH VERILOG
(COMMON TO ECE, BME, ECC)Time: 3hours Max.Marks:80
Answer any FIVE questionsAll questions carry equal marks
- - -
1.a) Explain the components of a verilog Module with block diagram?
b) Differentiate between simulation and synthesis? [8+8]
2.a) Design a T flip op using NAND gates.
b) Write a verilog code for T flip op using NAND gates. [8+8]
3.a) Explain about case statements with its observations.
b) Write verilog code using case statement for any one example. [8+8]
4.a) Explain continuous assignment structures with examples.b) Explain combining assignment and net declarations with examples. [8+8]
5.a) Explain Type Declaration for parameters.b) Explain specify mode of path delays. [8+8]
6.a) Explain Dice game with block diagram.b) Explain Dice game using flow chart. [8+8]
7.a) Explain combinational logic operation of XC3000 FPGA.
b) Explain XC3000 series FPGA flip flop with clock enable. [8+8]
8. Explain UART Design:a) Serial Data Transmission.
b) Standard Serial Data format.
c) Block diagram. [16]
-oOo-
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SET-2R05Code.No: R05420402
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.TECH II SEMREGULAR/SUPPLEMENTARY EXAMINATIONS MAY - 2010
DIGITAL DESIGN THROUGH VERILOG
(COMMON TO ECE, BME, ECC)Time: 3hours Max.Marks:80
Answer any FIVE questionsAll questions carry equal marks
- - -
1.a) What are the basic components of a module?
b) Which components are mandatory? [8+8]
2.a) Design module and a test bench for a half-adder?
b) Design module and a test bench for a 4 to 1 multiplex module? [8+8]
3.a) Explain about multinary branching.
b) Explain about loops and classify. [8+8]
4.a) Explain about operator priority with examples.b) Explain bit widths of expressions. [8+8]
5.a) Explain module paths.b) Design verilog module using of path delay. [8+8]
6.a) Explain SM chart for Dice game.b) Design state graph for Dice game controller. [8+8]
7. Explain parallel adder-subtractor with logic cell. [16]
8. Explain UART Receiver with SM Chart. [16]
-oOo-
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SET-3R05Code.No: R05420402
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.TECH II SEMREGULAR/SUPPLEMENTARY EXAMINATIONS MAY - 2010
DIGITAL DESIGN THROUGH VERILOG
(COMMON TO ECE, BME, ECC)Time: 3hours Max.Marks:80
Answer any FIVE questionsAll questions carry equal marks
- - -
1. Explain the following "lexical conventions" with examples.
a) Identifiers
b) Stringsc) Strengths
d) Logic values [16]
2.a) Design a module for addition of 16 bit words?
b) Write verilog module for addition of 16 bit words? [8+8]
3.a) Design verilog module to identify the highest priority interrupts.b) Write test bench, simulation results of above question with explanation. [8+8]
4.a) Design verilog module for 4 bit full adder using data flow operators.b) Design verilog module for 4 bit full adder with carry look ahead. [8+8]
5.a) Design verilog module use of specify block to specify out rise end full timeseparation for pin to pin delays.
b) Write test bench and simulation for the above. [8+8]
6.a) Design Dice game with test bench.
b) Design Dice game test module. [8+8]
7.a) Explain about XC4000 implementation of multiplier control.
b) Write differences between FPGA and CPLD. [16]
8. Design HDL module for UART Receiver. [16]
-oOo-
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SET-4R05Code.No: R05420402
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.TECH II SEMREGULAR/SUPPLEMENTARY EXAMINATIONS MAY - 2010
DIGITAL DESIGN THROUGH VERILOG
(COMMON TO ECE, BME, ECC)Time: 3hours Max.Marks:80
Answer any FIVE questionsAll questions carry equal marks
- - -
1.a) Explain simple latch with verilog module?
b) Explain RS Flip-op with verilog module and Test Bench? [8+8]
2.a) Design a half substractor module and use it to form a 4 bit substractor module?
b) Write verilog module for half substractor module and use it to form a 4 bit substractor
module? [8+8]
3.a) Design module to convert angle in radians to one in degrees.
b) Write verilog code above question with explanation. [8+8]
4.a) Design half subtractor using CMOS switches.
b) Write the verilog code for half substractor using CMOS switches. [8+8]
5.a) Design the use of group delay with an ALU module.
b) Write test bench and simulation results for the above. [8+8]
6.a) Explain PLA realization of SM charts.
b) Explain PLA table for multiplier control. [8+8]
7. Explain about CPLD Altera 7000 series. [16]
8. Write HDL Code for complete 486 Bus system with static RAM. [16]
-oOo-
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