Process Simulation for 65 nm - SMDPII-VLSI:Special ... Process Simulation for 65 nm By ... Hierarchy...

Harish B.P. Microelectronics Lab, ECE, IISc 8 December 2006

Process Simulation for 65 nm

ByHarish B.P.

Microelectronics Lab,Dept. of Electrical Communication Engg.,

Indian Institute of Science, Bangalore.E-mail: harish@ece.iisc.ernet.in

Outline

• Introduction• Mechanism of process simulation• DIOS process simulator• Modeling and simulation of semiconductor processes• Case Study: Simulated 65 nm NMOS• Summary

Introduction: Why Process Simulation?

• Computer simulation is now an essential tool for research and development of semiconductor process and device.

• Costs can be dramatically reduced by using simulation instead of experimentation, as much as possible, to fine-tune the process recipe.

• Shorter process development cycle.

Hierarchy of Simulation Tools

Parameters for a. Oxidation, b. Ion implantation, c. Diffusion

SPICE parameters:VT, Tox, Ion, Ioff, SS, γ, Netlist

Delay, Power, NM

Process Simulation

Device Simulation

Circuit Simulation

Eq.s for a. Oxidationb. Ion implantationc. Diffusion

Tox, Xj, Tsp, TgateNa, Nd

Poisson’s Eq.Continuity Eq.

Nodal Eq. KCL, KVL

(Circuit Performance)

Process Simulator

• Inputs to process simulation: lithography mask pattern, implantation dose and energy, temperatures and times for oxidation and annealing steps, etc.

• The process simulator generates a 2-D or 3-D structures with all the deposited or grown and etched thin films and doped regions.

• The output may be fed into a device simulator as input together with applied voltages, to evaluate the device electrical characteristics.

• Process/device is designed and optimized to meet the device design specifications, by process and device simulation based design approach.

Outline

Process Simulation - Mechanism

Space - time discretization• Represents device cross-section into a small cell.• Time discretization - Evaluate physical/chemical change

at each cell at every discrete time step.• Space discretization - Increment time step, update the

physical structure at each cell.• Moving boundary problem:

- Changing chemical composition at several mesh points- Simultaneous update Ex. Dynamically changing boundaries during oxide growth.

Space Discretization

• The device cross section is represented as the collection of small cells .The various quantites such as φ, n, p etc are constant within the cell.

• Granularity of discretization: meshing - fine or coarse• Mesh must be densest in device regions where

- current density is high (MOS channels, bipolar base)- electric fields are high (MOS channels, drain, depletion regions)- charge generation is high (SEU alpha particle)

• Dynamic mesh re-adaptation – when a parameter varies by an order of magnitude from one mesh point to next.

Time Discretization

• Discretize the time instants at which each cell is evaluated for its physical and chemical composition.

Control Commands

• To select physical models for processes and their respective parameters

• Gridding/meshing strategies• Graphical output preferences

Process simulators

1. T-SUPREM-IV from Stanford University (TAURUS- TSUPREM-IV from Synopsys)

2. Prophet from Bell Labs. 3. Florida Object Oriented Process Simulator (FLOOPS)4. DADOS5. Sentaurus Process from Synopsys6. SSuprem4 from SILVACO7. DIOS from Synopsys

Outline

Introduction to DIOS• DIOS is a multi-dimensional process simulator.• Supports simulations of complete fabrication sequences

– oxidation, diffusion, ion implantation, deposition/ etching, with models in 1-D and 2-D.

• Fully automatic meshing through adaptive grids.• Linear and non-linear solvers allow for simulation of

complex structures – 10,000 to 100,000 grid points.• Crystal-TRIM: 1-D and 2-D Monte Carlo simulator • Interface to 3-D Monte Carlo simulator - MCimpl.• Applicable to VLSI CMOS, power devices and advanced

SOI technologies.• Used with device simulator DESSIS to run and optimize

complete simulation flows.• Platforms supported: All UNIX flavours (Linux, Sun, HP,

IBM, SGI), Windows NT.

DIOS (contd.)

• Process flow simulated - sequence of commands corresponding to individual process steps.

• Procedure:- interactive mode: entered from standard input, at the prompt in command window.- composed in a command file.

Outline

• Introduction• Mechanism of process simulation• DIOS process simulator• Modeling and simulation of semiconductor

processes• Case Study: Simulated 65 nm NMOS• Summary

Modeling and Simulation of Semiconductor Processes

• Oxidation• Ion implantation• Diffusion

Oxidation• Classification : 1. Growth

2. Deposition

• Growth of SiO2: T > 800oCHeat Si wafer in steam (Wet oxidation)

- in dry O2/N2 mixture (Dry oxidation) at temperatures –800 to 1250o.Dry oxidation: Si + O2 SiO2 ( Tox < 100 – 200nm)Wet oxidation: Si + 2H20 SiO2 + 2H2

• Deposition of SiO2: T < 600oCChemical Vapour Deposition:

SiH4 + O2 SiO2 + 2H2

Modeling and simulation: Oxidation• Deal-Grove oxidation model:

Tox2 + ATox = B (t+τ) for Tox > 20 nm

Tox =BA

(t + τ) for Tox < 20 nm

where Tox = oxide thicknesst = oxidation timeB = parabolic rate constant

B/A = linear rate constantτ = native oxide dependent constant

Simulated oxidation parameters : 1. Thickness or time 2. Temperature3. Ambient4. Partial pressure

Program for oxidation• TITLE (“oxidation”)

grid (x=(0.0,0.4) y=(-1.0,0.0),nx=2)substrate (orientation=100, elem=B, conc=5E14, ysubs=0.0)

replace (control (ngra=10))graph (triangle=off, plot)breaka. comment (‘dry oxidation’)

diff (time=8s, temper=900, atmo=O2, po2=1)b. comment (‘wet oxidation’)

diff (time=8s, temper=900, atmo=H2O)c. comment (‘oxide deposition’)

depo (ox, thick=16nm)

Ion Implantation

• Beam of energetic ions implants dopants into the substrate.

• Depth and dopant concentration controlled by acceleration energy (implant energy) and beam current (implant dose) respectively.

• Dopant profile – Gaussian• Implantation produces crystal damage – anneal at 700 to

1000oC.

Modeling and simulation: Ion Implantation

• Implantation is simulated by using:1. Analytical distribution functions – experimental implantation tables2. Monte Carlo simulation to compute implant distribution and implant damage.

• Simulated primary parameters: Implant species, implant energy and implant dose

• Simulated secondary parameters: Tilt, rotation (related to wafer)

Program for Ion Implantation• TITLE (“implantation”)

comment (‘Ion implantation’)grid(x=(0.0,0.4) y=(-1.0,0.0),nx=2)substrate (orientation=100, elem=B, conc=5E14, ysubs=0.0)replace (control(ngra=10))graph (triangle=off, plot)breakimplant (element=P, dose=2E13, energy=300keV, tilt=0)

• elements: B, As; tilt: 6, 9,30.

Diffusion• Diffusion - Dopant redistribution caused by dopant and

point defect diffusion by chemical reactions at interfaces and inside layers by convective dopant transport due to

a. internal electrical fields, b. material flow and c. moving material interfaces.

• Diffusion takes place during all high temperature processes.

• Process atmospheres – O2, N2, H2O, H2O2.• Diffusion is simulated on the basis of point defect

models.

Modeling and simulation: Diffusion• Fick’s I law of diffusion:

Diffusion flux density F = -D ∂ C(x)

• Fick’s II law of diffusion:

∂ C(x,t) ∂ F(x,t) D ∂2 C(x,t)

∂x∂t= -

∂x2=

where D = Diffusivity (cm2/sec)C(x) = Vol. conc. gradient at x

F = Diffusion flux density (No. of particles/cm2-sec)Simulated diffusion parameters : 1. Time

2. Temperature3. Ambient4. Partial pressure

Program for Diffusion• TITLE(“Diffusion”)

comment (‘diffusion’)grid(x=(0.0,0.4) y=(-1.0,0.0),nx=2)substrate (orientation=100, elem=B, conc=5E14, ysubs=0.0)replace (control(ngra=10))graph (triangle=off, plot)breakdepo (material=P, thickness=10nm)DIFFusion (time=10s, temperature=1050degC, atmo=N2, po2=0.75)

Program for Annealing of DopantImplants

• TITLE (“implantation”)comment (‘Ion implantation’)grid(x=(0.0,0.4) y=(-1.0,0.0),nx=2)substrate (orientation=100, elem=B, conc=5E14, ysubs=0.0)replace (control(ngra=10))graph (triangle=off, plot)implant (element=P, dose=2E13, energy=300keV, tilt=0)breakDIFFusion (time=10, temperature=1050degC)

Outline

Full Program for simple NMOS

• TITLE (“65 nm NMOS example”)grid (x=(0.0,0.2325) y=(-10,0.0), nx=2)

substrate (orientation=100, elem=B, conc=1E16, ysubs=0.0)

replace (control (ngra=10))graph (triangle=on, plot)

Program (contd.)

comment (‘p-well, anti punch-through and Vt implants’)

implant (element=B, dose=2E12, energy=200kev, tilt=0)

implant (element=B, dose=1E12, energy=100kev, tilt=7)

implant (element=In, dose=5.7E12, energy=150kev, tilt=7)

comment (‘p-well: RTA of channel implants’)

diff (time=10s, temper=1050)

Program (contd.)comment (‘gate oxidation’)

diff (thickness=1.35nm, temper=800, atmo=O2, po2=0.75)

comment (‘poly gate deposition’)deposit (material=po, thickness=100nm)

comment (‘poly gate pattern’)mask (material=resist, thickness=800nm,xleft=0, xright=0.0325)

comment (‘poly gate etch’)etch (material=po, stop=oxgas, rate (anisotropic=100))

etch (material=ox, time=0.5, rate (aniso=10))

etch (material=resist)

Program (contd.)

comment (‘poly reoxidation’)diffusion (temp=(700,800), temprate=3000, atmo=N2)diffusion (time=4.5s, temp=800, atmo=O2, po2=0.5)diffusion (temp=(800,700), temprate=3000, atmo=N2)

comment(‘initial nitride spacer’)depo (material=ni, thickness=96nm)etch (material=ni, remove=96nm, rate(aniso=75))

Program (contd.)

etch (material=ni, stop=pogas, rate(aniso=10))

comment (N+ impl. and 20 sec RTA)impl (element=As, dose=6E15, energy=20keV, rotation=0, tilt=0)diff (time=20s, temp=1050, atmo=N2)

Program (contd.)comment (‘dispose spacer’)

etch (material=ni)comment (‘overlap control spacer’)

depo (material=ni, thickness=14nm)etch (material=ni, remove=14nm, rate(aniso=75))

Program (contd.)comment (‘nldd implantation’)

implant (element=As, dose=1E15, energy=5keV, rotation=0,tilt=0)

comment (‘Quad halo implant’)impl (element=B, Funct=Gauss, dose= 3.5E12,energy=8keV,rotation=0,tilt=30)

impl ( ,, rotation=90 ,,)impl ( ,, rotation=180 ,,)impl ( ,, rotation=270 ,,)

comment (‘screening oxide’)depo (material=ox, thickness=10nm)

comment (‘spike anneal’)diffusion (time=4sec, temp=1050, atmo=N2)

Program (contd.)

comment (‘final nitride spacer’)depo (material=ni, thickness=40nm)etch (material=ni, remove=40nm,

rate(a1=75))

comment (‘etching screening oxide’)etch (material=oxide, stop=sigas,

rate (aniso=75))

Program (contd.)

comment (‘full device structure”)reflect (window (bottom=-0.5)reflect (reflect=0.0)

comment (‘metal s/d contacts’)mask (material=al, thick=0.03, x(-0.2325, -0.1325, 0.1325, 0.2325))

Program (contd.)comment (‘oxide fill’)mask (material=resist, thick=800nm, x((-

0.2325, -0.1325, -0.0325,0.0325, 0.1325, 0.2325))

depo (material=ox,dtype=fill)etch (material=ox, remove=728 nm)etch (material=resist)

Comment (’save final structure for device simulation’)

save ( file=’nmos’, type=mdraw, synonyms (po=metal, al=metal))

contacts (contact1(name=’source’, -0.1825, 0.01)

contact2(name=’gate’, 0.0, 0.05)contact3(name=’drain’, 0.1825, 0.01)contact4(name=’subs’,loc=bottom)

Input/Output Files of DIOS

• Input files:- filename.cmd – sequence of commands for processes.

• Output files:1. nmos_mdr.bnd – final region boundary descriptions.2. nmos_mdr.cmd – set of commands for MDRAW (meshing tool).3. nmos_dio.grd.gz – contains DIOS grid.4. nmos_dio.dat.gz – contains DIOS doping data.

DIOS Generated Devices

a. NMOS b. PMOS

Outline

Summary

• Significance and mechanism of semiconductor process simulation is discussed.

• Modeling and simulation of various processes like oxidation, ion implantation and diffusion are described.

• A case study of generation of 65 nm NMOS is presented.

Thank You

Process Simulation for 65 nm - SMDPII-VLSI:Special ... Process Simulation for 65 nm By ... Hierarchy...

Documents

Transcript of Process Simulation for 65 nm - SMDPII-VLSI:Special ... Process Simulation for 65 nm By ... Hierarchy...

11°30'0W 11°0'0W K en m aD is tr c M p 3 5 . 7 kk Th is m ... · nm nm nm nm nm nm nm nm nm nm nm nm nm nm nmnm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm

An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm ...

14 nm Process Technology: Opening New Horizons · 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 14 nm 10 nm $ / Transistor (normalized) Cost per Transistor 35 Intel 14 nm continues to deliver

Radiation tolerance of 65 nm technology

Gate - images.landsofamerica.com"nm nmnm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm Þ B u l l T o n g u e C r e k West E n d S l o u g h B a ti s e C r e ek T-3 94 Ac

Addressing SWaP Challenges in Military Platforms With 65 ... · Addressing SWaP Challenges in Military Platforms With 65-nm FPGAs and Structured ASICs Altera Corporation 4 HMS Form

COMPUTER SIMULATION OF CAR AERODYNAMIC PROPERTIES · Computer Simulation of Car Aerodynamic Properties. Acta Universitatis Agriculturae et Silviculturae Mendelianae Brunensis, 65(5):

Antennas, Propagation 1 and Transceiver IC · PDF fileSystem (Sony) System Spec. IC ... (Tokyo Tech + Company) 90 nm 43 mm2 600 mW 90 nm 98 mm2 450 mW 65 nm 38 mm2 ... History of CMOS

GPU implementation of Cell Dynamics simulation for block ... · Correlation between theory, simulation and experiment ~1-1000 nm GPU implementation of Cell Dynamics simulation for

Ward / Quartier 1...$K $K $K $ $K!C nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm …

Numonyx Embedded Flash Memory (J3 65 nm) Single Bit …/media/Documents/Products... · Legal Lines and Disclaime rs8000 S. Federal Way, P.O ... Embedded Flash Memory (J3 65 nm) Single

InnerLinks Modular Wall Penetration Seals 4 pipes · InnerLinks Modular Wall Penetration Seals 4 pipes ... NBR rubber green ... IL 500 up to IL 575 65 Nm 50 Nm

NM - calpeda-pump.com · nm 10 50 hp 2 65 2 hp 2 50 2 hp hp kw kw $ ˘ n ./.

65 nm CMOS technology in High Energy Physics Pierpaolo Valerio CERN

Lithography Roadmap - Coocanaset.la.coocan.jp/event/ifst2005/S2-1_Litho-Road_IMEC_NO2.pdf · © imec 2005 Lithography Roadmap without immersion lithography 180 nm 130 nm 90 nm 65

FUEL LOSS ALERT STATUS - Al Bahar · NM NN M N NM N NM NM NN M NM NM NM MN M N NM NM NM MN M N NM MN N N N N MN NM NM NM M N MN MN M N N MN MN N NN PM DUE Maintenance | Utilization

NM KELURAHAN NOP THN NM WP SPPT NOMINAL 1 …pulosari-jombang.web.id/assets/files/dokumen/DHKP_2017.pdf · 65 pulosari 351707001200100720 2017 kadir p sumbru 32,260 66 pulosari 351707001200100730

Design tools and foundry access service plans for 65 nm technologies

Lawr enc , KSnm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm nm Õ" ñ k k k k ñ k s s s s s J^ L a k e View L ake Lake Alvamar K a n s a s r R i v e r Mary's Lake

Numonyx Embedded Flash Memory (J3 65 nm) Single Bit … Sheets/Micron Technology Inc... · 9.6 Suspend and Resume ... Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell