PLL Building Blocks Part 2 - TI Training

PLL Building Blocks Part 2 TI Precision Labs – Clocks and Timing

Presented by Dean Banerjee

Prepared by Liam Keese

R Divider

Output DividerReference

Oscillator

VCOLoopFilterPhase

Detector/Charge Pump

N Divider

KPD Z(s)fOUT

Phase lock loop (PLL) overview

fOSC fPD

fN fVCO

Input sources

R Divider

Oscillator

VCOLoopFilterPhase

N Divider

KPD Z(s)

• Crystal oscillator (XO)

• Temperature compensated crystal oscillator (TCXO),

• Oven controlled crystal oscillator (OCXO),

• Clock output from another device

tRESET

OUTPUT

Source

Current

Phase frequency detector/charge pump

R DividerReference Oscillator

VCOLoopFilterPhase

N Divider

KPD Z(s)

• High Impedance (tri-state) if output frequency/phase is correct (within tolerances)

• Sources Current if output frequency/phase is too low

• Sinks Current if output frequency/phase is too high

Phase Frequency Detector/Charge Pump Phase detector/charge pump operation

Loop filter

• The loop filter is a low pass filter

– Has a dramatic effect on performance

R Divider

Oscillator

VCOLoopFilterPhase

N Divider

KPD Z(s)

Brief overview of loop dynamics

R Divider

Oscillator

VCOLoopFilterPhase

N Divider

KPD Z(s)

Kvco/s

Choosing loop bandwidth

• Choose optimal jitter loop bandwidth to be BWJIT to minimize area under the

Choosing loop bandwidth

Design Goal Bandwidth

Minimize Jitter BW = BWJIT

Minimize Phase Noise at

offset < BWJIT

BW > BWJIT

Minimize Phase Noise at

offset > BWJIT

BW < BWJIT

Minimize Lock Time BW > BWJIT

Minimize Spurs BW < BWJIT

To find more technical resources and search products, visit ti.com/clocks

Short Quiz

1. True or False:

The reference input frequency is provided by VCO.

Short Quiz

1. True or False:

The reference input frequency is typically fixed frequency and provided by a stable reference

source such as crystal oscillator.

Short Quiz

2. Choose one:

The phase detector will

(a) Sink and source current to the loop filter

(b) Sample the phase error between the R and N counter

(c) Provide the output frequency

Short Quiz

2. Choose one:

The phase detector will

(a) Sink and source current to the loop filter

(b) Sample the phase error between the R and N counter

(c) Provide the output frequency

Short Quiz

3. True or False:

Choose loop bandwidth to be the point where VCO noise is equal to PLL noise to minimize jitter.

Short Quiz

3. True or False:

Choose loop bandwidth to be the point where VCO noise is equal to PLL noise to minimize jitter.

Short Quiz

4. Choose all that apply:

When choosing a loop bandwidth, which of these tradeoff are correct?

a) To reduce lock time, increase the loop bandwidth

b) To reduce spurious noise, increase the loop bandwidth

c) To reduce phase noise at larger frequency offsets, reduce the loop bandwidth

Short Quiz

4. Choose all that apply:

When choosing a loop bandwidth, which of these tradeoff are correct?

a) To reduce lock time, increase the loop bandwidth

b) To reduce spurious noise, increase the loop bandwidth

c) To reduce phase noise at larger frequency offsets, reduce the loop bandwidth

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PLL Building Blocks Part 2 - TI Training

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