Ofdm (Main Project ) VHDL SIMULATION & SYNTHESIS

VHDL SIMULATION & SYNTHESIS

OF OFDM Spread Spectrum TRANSMITTER/RECEIVER

Team membersShafeek H 07402066Vinod V 07402144Sanjay kumar 07402064Mahesh sankar 07402046

SIMULATION and SYNTHESIS

Simulation is used to verify the

functionality of the circuit.

Synthesis tools convert the design

description into equations or

components to fit into the target

technology.

Typical simulation waveform

Typical synthesis result

Presentation Outline

►OFDM-Introduction►Block Diagram►Scope of project►Project scheduling►Challenges►Design & Implementation►References

►Multi channel/carrier

modulation(MCM)- wideband channel to N non-ISI

AWN sub-channels by orthogonal basis functions to combat

the effects of multipath fading.

►DFT based MCM(DMT)- wideband channel to N

infinite non-ISI AWN sub-channels by orthogonal basis

functions for DSL

►DFT based MCM(OFDM)- Wireless DMT. In

OFDM, each sub-carrier is orthogonal to all other carriers.

However, this condition

is not always maintained in DMT. A data stream is divided

into several parallel streams before transmission.

What is Multipath?

Received signal is the sum of many versions of the transmitted signal with varying delay and attenuation. Cause ISI.OFDM is a solution to multipath.

What is ISI & ICI ?ICI(Inter channel Interference) occurs when independent data streams on two or more channels interfere with each other.

ISI(Inter symbol Interference) occurs on a single channel when a symbol is interfered with by either its predecessor(s) or its successor(s). Frequenct offset.

Frequency offset can shift the received signal

FDM Vs. OFDMFDM OFDM

Unique carrier for each data(single carrier per spectrum)

Data distributes over sub-carriers(spread spectrum).Data is transmitted in parallel on sub-carriers.

Carriers spaced far apart.Non-overlapping signal spectra

Sub-carriers spaced apart at precise frequencies.Overlapping signal spectra

Low spectral efficiency High spectral efficiency

Use in 2G,3G Use in 4G

OFDM Spectrum

overlapping sub-channels

Overlapping reducing the required bandwidth but keeping the modulated signals orthogonal so they do not interfere with each other.

Orthogonality of sub-carriers

The spectrum of each sub-carrier has a “null” at the centre

frequency of each of the other sub-carriers in the system. This

overcomes the problem of overhead carrier spacing required in

FDMA. Each sub-carrier has an integer number of cycles over a

symbol period. Sub-carrier spacing provides the "orthogonality“,

which prevents the demodulators from seeing frequencies other

than their own.

Sin(x)/x spectra

Basic Mathematical Principle of ‘analog’ OFDM

Product modulator

Sub-carrier

Separate local oscillators to generate each individual sub-carrier.

‘Analog’ OFDM System Correlation Receiver

Discrete OFDM

Stje 0w+

tj Ne 1-+ w

1, -Nns

.. . Parallel to Serial

(P/S) IDFT.. .0,ns

1, -Nns

Basis function

Orthogonality by FourierIDFT

twiddle factorFFT

N=2,radix 2

IFFT that basically gives OFDM its

orthogonality. The sub-carriers can now

be generated using IDFT. The FFT can

keep tones orthogonal to one another if

the tones have an integer number of

cycles in a symbol period.

Orthogonality by Fourier

Features of OFDM Scheme► Maximum spectral efficiency► Flat fading per carrier and hence high speed

equalization is avoided and only N short equalizers are needed

► N long pulses and hence multi-path has less impact on implementation.

► ISI,ICI is comparatively short and narrow band interference has less impact as orthogonality.

► Easy implementation using FFT and hence no bank of sub- carrier oscillators and coherent demodulators.

► FDM is achieved by base band processing and not band pass filtering.

OFDM Disadvantages►High peak-to average-power ratio

(PAPR) This put high demand on linearity in amplifiers.

►Phase noise error and Doppler shift cause degradation to OFDM system

►Very sensitive time frequency synchronization

APPLICATIONS OF OFDM

►digital audio broadcasting (DAB)►terrestrial digital video broadcasting

(DVB)►ADSL,HDSL►WiMAX► use in future fourth generation (4G)

networks. ►for power line communications

systems►MB-OFDM in UWB

OFDM Transceiver Block Diagram

coding

IFFT (Tx)

De-interleaving

QPSKdemapping

Parallel to serial

Serial toparallel

Remove cyclic Extension

Decoding

Interleaving

QPSKmapping

Serial toparallel

Parallel to serial

Add cyclic Extension and windowing

Output of transmitter

Input to receiver

FFT (Rx)

Data input to the transmitter

Data received

Scrambler

AddPilots

Synchronisation

Channel EstimateEqualizer

DeScrambler

convolutional

-viterbi

Guard Interval

SCRAMBLER / DESCRAMBLER- To make the input sequence more

disperse(randomizes) so that the dependence of input signal’s

power spectrum on the actual transmitted data can be

eliminated.

Scrambling is a technique used to randomize a data stream to

eliminate long '0'-only and '1'-only sequences and to assure

energy dispersal. Long '0'-only and '1'-only sequences create

difficulties for timing recovery circuit.

ADDITION / REMOVAL OF CYCLIC PREFIX- In order to preserve the sub-

carrier

orthogonality and the independence of subsequent OFDM symbols, a

cyclic guard interval is introduced. Addition of cyclic prefix results in

circular convolution between the transmitted signal and the channel

impulse response.

Remove ISI, ICI by providing the delay spread in the channel is less

than the guard period. OFDM system resistant to time dispersion.

Guard interval to eliminate ISI

The guard interval will reduce the information rate.

INTERLEAVER / DE-INTERLEAVER- The bits(128b for 64 sub-carrier)

within an OFDM symbol are re-arranged in such a fashion so that

adjacent bits are placed on non-adjacent sub-carriers. Thus, protect

the data from burst errors. As a result of interleaving, correlated

noise introduced in the transmission channel appears to be statistically

independent at the receiver and thus allows better error correction.

EQUALIZER- To avoid multi path fading effects. If the number of sub-

channel is large enough, the channel can be viewed as flat fading. Then

a one-tap equalizer is sufficient.

Pilots- The pilot symbols are used in wireless communication systems

for the sake of channel estimation and correction purposes. For 64

subcarriers case in 802.11a the 4 pilots positions is -21,-7,7,21.

QPSK- Data is carried by varying the phase of each subcarrier.

Phase Data

45 degrees Binary 00

Scope of the Project

►VHDL programming

►ModelSim for Simulation

►Xilinx ISE for Synthesis

Project design flow

JAN.full month

FEB.full month

MAR.first week

MAR.second week

Top level design

Creating logic for each block

RTL Description of design functionality in VHDL

Simulation

Synthesis

I/O Integration of the blocks

FPGA Implementation

RTL uses flip-flops, arithmetic-logic-units and multiplexers interconnected by wires. Optimized net list can be programmed directly into a FPGA chip.

challenges

X(k) = x(n) WN n k

Here, WN = exp (-j2/N)

Radix-2 Decimation In Time algorithm: n=N/2 –1 n=N/2 –1

X(k)= x(2n)WN/2nk + WN

k x(2n+1)WN/2nk

n=0 n=0

1. FFT/IFFT algorithm implementation

Cooley–Tukey

Most important step in the OFDM communication system.

X(k) = x(n) WN n k

Here, WN = exp (-j2/N)

Radix-2 Decimation In Time algorithm: n=N/2 –1 n=N/2 –1

X(k)= x(2n)WN/2nk + WN

k x(2n+1)WN/2nk

n=0 n=0

2. FPGA implementation

These logic will not fit into one FPGA in the boards

that we have in our college, thus we wont be able to

implement FPGA hardware.

Higher end boards to map the design to targeted

device (Altera Cyclone III starter board) themselves

cost more than Rs.50000/- which is very expensive.

3. Factors definition

►data rate►bit rate► convolutional code rate►noise immunity

We have to define,

TRANSMITTER DESIGN AND IMPLEMENTATION

SCRAMBLER(randomizer)

In the proposed design, a standard 7 bit scrambler has been used to randomize the incoming bits.

CONVOLUTIONAL ENCODER

Initially all zeroes are stored in the register.

m=1, n=2 and k (constraint length) =7

INTERLEAVER

Two memory elements (usually RAMs) are used. In the first RAM the incoming block of bits is stored in sequential order. This data from the first RAM is read out randomly (using an algorithm) so that the bits are re-arranged and stored in the second RAM and then read out.

The three building blocks of the interleaver are: • Block Memory • Controller • Address ROM

The job of the controller is to guide the incoming block of data to the correct memory blocks, to switch the RAMs between reading and writing modes, and to switch between the two RAMs for 16 alternate bits in writing mode. This is done by using counters.

The address ROM is basically a 64x6 ROM that stores read addresses for the RAMs.

Counter C is a 3-bit counter that controls switching between either RAM 1A and RAM 2A or RAM 1B and RAM 2B depending upon which RAMs are in write mode. Counter1 and Counter2 are 5-bit counters after every 8thcount control switches to either Counter1 or Counter2; this is controlled by Counter C.

CONSTELLATION MAPPER

Signal constellation of QPSK

* * * *

-3m/8 -m/8 m/8 3m/8

* * * *

In QPSK two bits make up one symbol.

Mapping of bits to constellation points

A ROM is used to store the constellation points. Each constellation

point is represented by 48 bits in binary. In these 48 bits, the

most significant 24 bits represent the real part and the least

significant 24 bits represent the imaginary part. In both the

real and imaginary parts the most significant 8 bits are the integer

part and the least significant 16

bits represent the fractional part. 2’s complement notation has

been used to represent negative numbers. The size of ROM is

The incoming input bits (2 bits) act as address for the ROM. Each

ROM values in the ROM is a constellation point corresponding to

the data bits which here act as addresses for the ROM.

Serial to Parallel module

The data comes serially from the input port SERIN. The

parallel data is output from DOUT port. Output port DRDY is

asserted ‘1’ when the start bit, 8 bit data and the parity bit

is received. Output port PERRn is asserted ‘0’ when the

parity bit received is different from the parity generated

inside the serial to parallel circuit. When parity error is

detected, the serial to parallel circuit would be reset before

its normal operation can be performed.

IFFT DESIGN64-point Radix-2^2 fixed-point DIT FFT

Since in the proposed design there are 64 sub-carriers so the input to FFT would be 64 complex numbers, hence a 64 point FFT would be required.

bf2i and bf2ii radix 2 butterflies

In our case there would be 3 stages (64 = 43) and 16 4 point DFTs per stage or we can say 16 butterflies pre stage.

The module consists of six radix-2 butterflies, shift registers

associated with each butterfly, two complex multipliers, two twiddle

factor generators, and a controller that provides the control signals.

The FFT Radix-2 butterfly must have two inputs in order to

produce the next FFT intermediate value, but the data in our

scenario is available only in a serial mode. The SDF(Single-path

Delay Feedback) mechanism provides a solution where the first

input is delayed until the second input is presented, after

which the calculation can proceed. Both the bf2i and bf2ii

modules accomplish this by multiplexing the first input to a

shift register of sufficient length so that that data-point is present

at the butterfly input when the second data-point appears. A

counter provides the control signals for these multiplexers, which

are internal to the butterfly modules.

Parallel to Serial module

A parallel to serial converter is a special function of shift

register. The data is parallel loaded to the shift register and

then shift out bit by bit also is bounded by a start bit and

stop bit.

Data to be transmit is first parallel loaded then transmitted bit by

bit by a start bit of value ‘1’. This is followed by the 8-bit data with

the left bit most bit first. The converter holds the output low when

the transmission is completed.

CYCLIC PREFIX ADDER

Causes intercarrierinterference (ICI)

If multipath delay is less than the cyclic prefixno intersymbol or intercarrier interference

The architecture of cyclic prefix adder simply consists of an

address ROM that stores addresses, a RAM to store incoming

data in sequential order and a counter that provides read

addresses to the RAM.

In the proposed design, the last eight symbols (complex numbers)

of the OFDM symbol are replicated at the beginning of the symbol,

therefore a total of 72 (64 + 8) symbols are actually transmitted.

Control unit

The control unit synchronizes

the operation all the blocks in

order to avoid any timing

mismatches.

RECEIVER DESIGN AND IMPLEMENTATION

The receiver follows an exact reverse procedure of which

followed in the transmitter. It receives the complex

(modulated) output points and performs demodulation and

recovers the original bits sent to the transmitter.

CYCLIC PREFIX REMOVER

The cyclic prefix was added at the transmitting end in

order to avoid inter-symbol interference, therefore during

reception it must be eliminated for any further processing of

the received signal. This is done by simply skipping the first

eight sub-carriers in the received OFDM symbol. In hardware

this is implemented in the control unit. The control unit only

enables the next block (FFT) when the first eight bits of the

received OFDM symbols have been skipped .

FAST FOURIER TRANSFORM

In order to implement FFT in hardware the

algorithm is same, only the difference is that

the divider is removed and the real and

imaginary parts at the input are swapped

i.e. real becomes imaginary and imaginary

becomes real. Same goes for the output i.e.

real and imaginary parts at the output are

swapped as well.

CONSTELLATION DE-MAPPER

Data points mapped to constellation points

Therefore, basically the incoming constellation points are mapped onto the data points as shown in Table. Can be implemented by direct coding.

DE-INTERLEAVER De-interleaving performs the inverse task. It re-arranges the

interleaved bits into their original order. De-interleaving is

done the same way as Interleaving, the difference being

that the number of rows and the number of columns for

de-interleaving are interchanged.

Hence the only difference in the hardware architectures of

interleaver and de-interleaver is the contents of the

address ROM, which actually provides the read addresses

to the RAM that stores the data to be de-interleaved.

DECODER

The Viterbi Decoder decodes Convolutional codes.

We are planning to use the Altera’s Viterbi Decoder

IP core in our design. Altera’s Viterbi IP core is a

parameterized IP core that is synthesizable and

allows for parallel as well as hybrid

implementation of the Viterbi decoder.

DESCRAMBLER

The above setup simply descrambles the scrambled data.

REFERENCES

► L. J. Cimini “Analysis and simulation of a digital mobile channel using orthogonal frequency division multiplexing.” IEEE .

► S. B. Weinstein and P. M. Ebert, “Data transmission by frequency-division multiplexing using the discrete Fourier transform”, IEEE.

► mathworld.wolfram.com/FastFourierTransform.html

► Wikipedia for Scrambler, Interleaver, Reed Solomon error-correction code, and Interleaver.

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