Post on 25-Apr-2018
NRAM: High Performance, Highly Reliable Emerging Memory Sheyang Ning1,2, Tomoko Ogura Iwasaki1,
Darlene Viviani2, Henry Huang2, Monte Manning2, Thomas Rueckes2,
Ken Takeuchi1
1Chuo University 2 Nantero Inc. Flash Memory Summit 2016 Santa Clara, CA
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Outline
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l Introduction of NRAM l Single NRAM cell and cell array measurement setup l NRAM characteristics
l DC-IV curve l Set and reset program characteristics l Large on/off ratio l High temperature program l High endurance
l Conclusion
Introduction of NRAM
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DRAM
NRAM
NAND flash
Nano-RAM, Carbon nanotube based resistive memory
Performance
Compare with Conventional Memories
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DRAM NAND flash NRAM
Performance
Scalability
Non-volatile
= bad = good
Endurance
20 ns pulse [1]
Single cell 15 nm [2]Single cell 1012 [3]1000 years@ 85ºC [2]
[1]. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 2014, pp. 96–97. [2]. Nantero Presentation for ITRS ERD/ERM, International Technology Roadmap for Semiconductors (ITRS), 2013. [3]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015.
Compare with Emerging Memories
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[1]. S. Ning et al., Solid-State Electronics, vol. 103, pp. 64–72, Jan., 2015. [2]. H. Y. Cheng et al., IEEE Int. Electron Devices Meeting, 2013, pp. 30.6.1–30.6.4. [3]. S. Ning et al., Symp. on VLSI Tech., 2014, pp. 96–97. [4]. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 2015, pp. 1198-1199.
ReRAM [1] PRAM [2] NRAM [3]
Endurance 108 109 1012
High Current High Low
Resistive switching on
readPhase change
Filament size
Tunneling current
between CNTs
Material Carbon nanotube (CNT)AlxOy Ge2Sb2Te5
Physical Mechanism
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[1]. S. Ning et al., in VLSI Symp. Tech. Dig., Jun. 2014, pp. 120–121. [2]. Nantero presentation, Int. Tech. Roadmap for Semiconductors (ITRS), 2013.
Small distance
R cell 800 kΩ
R cell ≈ 1 GΩ
Large distance
≈
Physical Mechanism
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Set: attraction force
+
−
Reset: repulsive force
Electrical induction
Heat caused phonon vibration
[1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015.
Outline
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l Introduction of NRAM l Single NRAM cell and cell array measurement
setup l NRAM characteristics
l DC-IV curve l Set and reset program characteristics l Large on/off ratio l High temperature program l High endurance
l Conclusion
Single NRAM Cell and Cell Array Test
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[1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015. [2]. G. Rosendale et al., Proceedings of the European Solid-State Circuits Research Conference (ESSCIRC), Sept. 2010, pp. 478–481.
140 nm NRAM single cell 116 nm, 4 Mbits NRAM cell array
NRAM testchip
SL0BL0
0 V+VSet
WL
+VReset0 VSet voltage
Reset voltage
SLNBLN
NRAM cell
BL SL
……
V d
V g
NRAM cell
Oscilloscope
Outline
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l Introduction of NRAM l Single NRAM cell and cell array measurement setup l NRAM characteristics
l DC-IV curve l Set and reset program characteristics l Large on/off ratio l High temperature program l High endurance
l Conclusion
-3 -2 -1 0 1 2 3
ResetSet
Vd (V)
I d(µA)
100
1
10−2
10−4
10
10−1
10−3
DC-IV Curve
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0 1 2 3Vd (V)
051015
I d(µA) Trigger
voltage
[1]. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 2014, pp. 96–97.
Current vibration due to long term voltage stress on CNTs
Single cell bi-polar program
Butterfly curve
Same cell, reset curve
-20
0
20
40
Cur
rent
(µA
) Voltage (V)
0.72pJ
Low Program Current
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Single cell DC Icompliance = 5 µA, 30 µA, and 100 µA
Single cell AC Ipeak < 20 µA
[1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015. [2]. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 2014, pp. 96–97.
Time (ns)0 50 100 150
Time (ns)0 50 100 150
Reset
Set
-40
-20
0
20
Cur
rent
(µA
) Voltage (V)0.57pJ
Voltage
Cur
rent
(A)
10−8
10−4
10−6
10−2
10−10
10−12
100 µA30 µA5 µA
Set Reset
ResetB
ER(a
.u.) 2
1
0
1 10.8
0.60.40.8
0.6
Reset Characteristic
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l Cell array measurement, Reset is driven by both voltage and current
[1]. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 2015, pp. 1198-1199.
WL=0.4 a.u., SL from 0 to 1 a.u.
SL=VprogramBL = 0 V
WL= Vgate
Set and Reset Voltages
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l Use incremental pulse programing on single cell
[1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015.
0.4
0.6
0.8
1
ResetvoltageSetvoltage(absolutevalue)
Write cycles106 107 108 109 101010111012
Prog
ram
vol
tage
s (a
.u.)
0.2
0.4
0.6
0.8
1
Write cycles106 107 108 109 101010111012
Prog
ram
vol
tage
s (a
.u.)
0%
20%
40%
60%
80%
100%
cell 1cell 2cell 3
Cum
ulat
ive
prog
ram
suc
cess
Reset voltage (V)Cum
ulat
ive
prog
ram
suc
cess
0%
20%
40%
60%
80%
100%cell 1cell 2cell 3
Cum
ulat
ive
prog
ram
suc
cess
Set voltage (V)Cum
ulat
ive
prog
ram
suc
cess
Reset Set
l Three randomly chosen NRAM cells
Large On/Off Ratio
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l Single cell measurement
[1]. S. Ning et al., IEEE Symp. on VLSI Technology, Jun. 2014, pp. 96–97.
Possible for multi-level cell (MLC) > 100 times on/off ratio
Read at 1 V
0 50 100 150 200Read cycles
Res
ista
nce
(Ω)
Resistance ≈ 1.3×107 Ω
≈ 105 Ω104
105
106
107
109
108
High Temperature Program
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l Single cell measurement, stable program voltage at different temperatures
[1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015.
2585125
Reset voltage (a. u.)
Res
et fa
ilure
rate
(a.u
., lo
g sc
ale)
10 0.5
2585125
Set voltage (a.u.)
Set f
ailu
re ra
te (a
.u.,
log
scal
e)
10 0.5
Reset Set
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High Endurance Single cell
[1]. S. Ning et al., IEEE Trans. on Electron Devices (TED), vol. 62, no. 9, pp. 2837–2844, Sept. 2015. [2]. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 2015, pp. 1198-1199.
Cell array
Write cycles
104
105
106
108R
esis
tanc
e (Ω
)
LRS ≤ 200kΩ
HRS ≥ 1.25MΩ
106 107 108 109 1010 10111012
107
Reset BERSet BER
Write cycles
Prog
ram
BER
(a.u
.)
5
4
3
2
1
0103 104 105 108106 107
High Endurance
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l Cell array does not wear-out after 108 write cycles
[1]. S. Ning et al., Japanese Journal of Applied Physics (JJAP), vol. 55, no. 4S, 2016. [2]. S. Ning et al., Ext. Abstr. Solid State Devices and Materials (SSDM), Oct. 2015, pp. 1198-1199.
1 2 3 4 5
Set BERSet BER afterSet voltage
SetBL voltage (a.u.)
108 write cyclesafter 103 write cycles
1
0.8
0.6
0.5
0.7
0.9
1
0
0.8
0.6
0.4
0.2SetB
ER (a
.u.)
Verify-set pulses1 2 3 4 5
Reset BERReset BER afterReset voltage
Reset SL voltage (a.u.)
108 write cyclesafter 103 write cycles
1
0.8
0.6
0.7
0.9
1
0
0.8
0.6
0.4
0.2Res
etB
ER (a
.u.)
Verify-reset pulses
Outline
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l Introduction of NRAM l Single NRAM cell and cell array measurement setup l NRAM characteristics
l DC-IV curve l Set and reset program characteristics l Large on/off ratio l High temperature program l High endurance
l Conclusion
Conclusion
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l NRAM is an emerging nonvolatile memory cell which has performance between DRAM and NAND flash.
l Compared with other emerging nonvolatile memories, NRAM has competitive characteristics, including, lower program current, large on/off ratio, large endurance, high temperature stability and long retention time.