Modeling of a Digital Protective Relay in a Real Time Digital Simulator

Normann Fischer, Member IEEE, Brian K. Johnson, Senior Member, IEEE,, , , , ,

John P. Stubban, Member IEEE, Yu Xia, Student Member IEEE

Outline

IntroductionIntroductionTest SystemSchematic ModulesSimulated Relay PerformanceSimulated Relay PerformanceSimulated and Hardware Relay ComparisonConclusionConclusion

IntroductionIntroduction

EMTP: H W Dommel set up a framework forEMTP: H. W. Dommel set up a framework for the simulation of electromagnetic transients in power systems using digital computers in 1969power systems using digital computers in 1969.RTDS: Merge the flexibility of EMTP and the real time operation of the analog simulatorreal-time operation of the analog simulator.Hardware in the Loop Test: Test relay response

di b P i d ito power system disturbances. Protective device has to be realized in hardware.

Test Systemy

Power Transformer: Verify stability of the y ydifferential element.Transmission Line: Evaluate impact of a longTransmission Line: Evaluate impact of a long line with shunt reactors.Power Sources: Control power flow faultPower Sources: Control power flow, fault current, out of step conditions.

S A id lIn-zone Surge Arrestor: Provide overvoltage protection for the power transformer.Current Transformers: Properly sized to verify stability of the relay.

Data Acquisition Moduleq

A l L P Filt B tt th filt ithAnalog Low Pass Filter: Butterworth filter with a cutoff frequency lower than the digitizing folding frequencyfolding frequency.Digital FIR Filter: Full cycle cosine filter, compromise between speed and performancecompromise between speed and performance.

Overall frequency response of the data i i i d lacquisition module

Overview of the sub-modules

5 sub modules in parallel: Detect internal fault re-classify a5 sub modules in parallel: Detect internal fault, re classify a potential fault as an external event.

Filtered Differential Module

IIIIvvv

+++:

F t l f lt t i ll ti t i

nFilterRT IIII +++= ...: 21_

IOP _ Filter :=

v I 1 +

v I 2 + ...+

v I n

For external fault, typically, operating current remains at 0, restraint current increases. For internal fault, both restraint and operating current increaserestraint and operating current increase.

Two Important Heuristicsp

Restraint Current Memory Element

Dual Slope Characteristic: Detected external fault will

IRTMk := Max(IRTk,0.15 ⋅ IRTk + 0.85 ⋅ IRTMk−1)

palce the relay into high security mode

External Fault Detection Module

Used to determine whether a fault is outside ofUsed to determine whether a fault is outside of the protective zone. The relay will be switched to a high security mode once this module is g yasserted. It is made up of four individual subsystems.

1. Raw operating and restraint module2. Raw delta operating and restraint modulep g3. Fault detection module4. Security module4. Security module

External Fault Detection ModuleExternal Fault Detection Module

External fault needs to be asserted prior to the CT saturation.Raw unfiltered current signals are used in this modulemodule.

1: −−= kkk IOPRIOPRDIOPR

Under normal operating conditions, the delta quantities 1: −−= kkk IRTRIRTRDIRTR

p g , qare very close to zero.If an internal fault occurs, both quantities will change.If the fault is external and no CT saturation occurs, only restraint current will change.If th f lt i t l d CT t ti CTIf the fault is external and CT saturation occurs, CTs should not saturate within the first two milliseconds after fault inception, and the amount of delta quantity e u cep o , d e ou o de qu yby the operating current will be much smaller than that generated by the restraint current.

Internal Fault Detection Module

Detect presence of solidly grounded internalDetect presence of solidly grounded internal faults, a high resistance to ground internal fault, and phase-to-phase faults inside the zone of p pprotection. The internal module consists of the following sub-blocks:

1, Raw restrained memory module2, Biased raw restrained module3, Comparator module4, Fault detection module4, Fault detection module

Internal Fault Detection Module

Raw Restrained Quantity: Supply the relay with the best t i t lrestraint value.

M lti l b bi i f t hi h i d d d lIRTMRk := max[IRTRk ,(0.15 ⋅ IRTRk + 0.85 ⋅ IRTMRk−1)]

Multiply by a biasing factor, which is depended on relay mode.

Internal fault sub-blocks

Sliding Window Module: Raw differentialSliding Window Module: Raw differential element RDIF is asserted if the raw operating quantity is greater than the biased raw restraint q y gquantity. RDIF will open a window during which if RDIF asserts again, WFAULT will assert.Conventional Timer Module: Conventional i d l h RDIF b hi h ftimer module, where RDIF must be high for a

fixed amount of time.

Directional Module

Di ti l M d l U d t lif th filt dDirectional Module: Used to qualify the filtered differential element module. It has three individual subsystems: Magnitude comparison module; directional y g p ;calculation module; directional comparison module.

Directional Module

Directional module calculates the direction ofDirectional module calculates the direction of the input currents with respect to a reference currentcurrent.

Th h h ld i l d h h h lTorque := Re(IREF ) • (IOP

* )

The threshold is scaled such that the angular difference between the reference current and the

i h b ll f lloperating current has to be smaller for small values of current than for larger values of current.

cIImThresholdTorque OPREF +••=:_

Open CT Detection ModulepA concern for protection engineers: one of the CT inputs becomes disturbed or lost entirely. Detection module mustbecomes disturbed or lost entirely. Detection module must be designed to distinguish between a fault condition and an open current transformer condition. It has two subsystems: Delta operating and restraint current module; Filtered operating current module.

Open CT Detection ModuleTable 1: Response of restraint anoperating current due to difference disturbances

Condition IOP (RAW) IRT (RAW) ΔIRT+ΔIOP (RAW)OP (RAW) RT (RAW) RT OP (RAW)

External fault, no CT saturation

Unchanged Increases > 0

External fault, with CT saturation

Increases Increases > 0

Internal fault, with no fault resistance

Increases Increases > 0

Internal fault, with high fault Increases Increases in most >0resistance cases

Open CT Condition Increases Decreases = 0

Simulated relay performancey pA. External Fault During an Out of Step ConditionRelay Response:y p1, High Security Mode;2, No trip Command.

B. Energization of a line reactor

R l RRelay Response:1, Disturbance classified as external;2, No trip command.

C. Solid Internal Fault

Relay response:Corresponding Relay elements picked up and issued a trip command.

D. Evolving Fault

Relay Response:1, External fault element asserted first;, ;2, WFAULT element asserted and release the external fault flag;3, Relay issued a trip command.

E. Open CT

Relay Response:1 CT open detection element asserted;1, CT open detection element asserted;2, Relay did not issue trip command.

Simulated and hardware relay performance icomparison

Test Name Characteristic Signal(s) Simulation Relay(ms) Hardware Relay(ms)

External Fault during an out-of-step

diti

CON1 4.2 4.3

condition

Line Energization CON1 4.0 5.0

Solid Internal Fault 87R 8.8 9.1

Evolving Fault CON1 2.4 2.587R 22.3 22.5

High impedance internal fault

87R 27.2 26.7

Conclusions

1, Performance difference between the simulated relay and hardware relay is within reasonable tolerance;y2, This makes it possbile to research ,develop, and verify protective algorithms without having to realize the relay in hardware first;hardware first;3, Enable relay designers to fine tune a proposed algorithm and know the limits of the algorithm performance;4, Now it is possible to predict how a protective device will react to a specific disturbance and strike a balance among reliability security and speedreliability, security and speed.