Post on 06-Apr-2018
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Mixed-Signal Systems-on-Chip:Architectures and Design Tools
Alex Doboli, PhD
Associate Professor
Department of Electrical and Computer Engineering
State University of New York, Stony Brook, NY 11794
Email: adoboli@ece.sunysb.edu
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The Wish List
A new development paradigm that:
Much more efficient design methodologies
Higher Level Of Abstraction For Development
Exploit design reusability & retargeting
Frees Designers From Low Level Implementation Detail
Produces Interoperable And Portable Designs
Supports Reconfigurability Provides Extensive, and Extensible, Third-Party Device
Libraries
Is Self-Documenting
Is scalable and extensible
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Research, Entrepreneurial & Educational
Challenges
High-level AMS synthesis?
Stephan Ohr, Synthesis proves to be Holy Grail
for analog EDA, EE Times, 06/08/1999
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Research, Entrepreneurial & Educational
Challenges
AMS design is art and less science
Theory? Methodology? How to invent application-
specific topologies & circuits?
Architectures?
Few CAD tools (mostly simulators: SPICE etc.)
Transistor is not a switch! (modeling)
Design usually at a low level (transistors, layout)
Who will develop the architectures & tools?
Who designs AMS systems? EE/CE/CS/all?
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Presentation outline
PSoC: embedded mixed-signal architecture
Related research at Stony Brook
Systematic methodology for ADC design Automated circuit modeling
Education & training
Conclusions
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Embedded Mixed-Signal Architectures
Cypress programmable PSoC mixed-signal SoC
Main features: Hardware programmability
Programmable analog blocks
Programmable digital blocks
Programmable interconnect
Programmable I/Os
Programmable clocks
Selectable power supply
Integration as an SoC
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PSoC Mixed-Signal Architecture
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Why PSoC-like architectures ?
PSOC supports/helps:
Design reusability & retargeting (library)
Predictable performance (library of models)
Frees designers from low level implementation(pre-characterized cells)
Supports Reconfigurability
Supports extensive, and extensible, third-partydevice libraries
Is scalable and extensible (programmable
transceivers, PLLs, software radio)
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PSoC Mixed-Signal Architecture
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PSoC Mixed-Signal Architecture
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PSoC Mixed-Signal Architecture
Analog blocks are programmable
Programmable functionality (control registers) Programmable inputs & outputs
Analog blocks of two types Continuous time blocks
Switched capacitor blocks (type C and type D)
Connected to programmable I/O ports
Programmable interconnect
Three kind of programmable interconnect
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Programmable interconnect
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Programmable CT blocks
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Programmable SC blocks
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PSoC Mixed-Signal Architecture
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Some CAD related Issues
Higher Level Of Abstraction For Development
What behavioral descriptions are synthesizable? DAEs, TFs,SFGs?
How do you correctly mix together continuous time and discretetime descriptions?
What standard specification notations? VHDL-AMS, Verilog-A,
MATLAB/SIMULINK, UML? Frees Designers From Low Level Implementation Details
How do you synthesize a set of DAEs? (application-specifictopologies)
Does the design work? (circuit modeling)
CAD tools for transistor sizing and layout (Neoliniar CADENCE)
Supports Reconfigurability Reconfigurable AMS architectures, reconfigurable ADCs, filters
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VLSI System Design Laboratory(http://www.ece.sunysb.edu/~vsdlab)
Lab director: Dr. Alex Doboli,
Email: adoboli@ece.sunysb.edu,
Phone: 631-632-1611
Lab expertise:
Embedded mixed-signal systems
CAD for system&circuit optimization
Analog circuit modeling IP core integration
Research funding (since 2001): NSF Center for Design of Analog
and Digital IC
AFRL
NSF ITR DARPA, IBM, DAC, Cypress
Academic results: 3 PhDs graduated
3 MS graduated
19 journal papers
65 peer reviewedconference papers
IC Developments: Rhapsody CADtool (ADC design)
ISIS CAD tool
(SoC integration)
SoC design in0.18m process
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VLSI System Design Laboratory(http://www.ece.sunysb.edu/~vsdlab)
G. Gielen, R. Rutenber, Computer-Aided Design of
Analog and Mixed-Signal Integrated Circuits,Proceedings of IEEE, Vol. 88, No. 12, pp. 1825-1852, 2000:
Recently, a first attempt was presented towards the fullbehavioral synthesis of analog systems from (annotated)
VHDL-AMS behavioral descriptions.
A. Doboli, R. Vemuri, "Behavioral Modeling for High-Level
Synthesis of Analog and Mixed-Signal Systems from
VHDL-AMS", IEEE Transactions on CADICS, Vol. 22, No.
11, 2003, pp. 1504-1520. (among the most downloadedpapers in 2005)
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Rhapsody: Automated design
of analog and mixed-signal systems
Topology generation and
system architecture selection:VHDL-AMS
specifications:entity aaa is
end entity;
Performance
evaluation
Circuit and
interconnect
models
Obtained
performanceConstraint transformation,
floorplanning and global routing
Performance
evaluation(simulation)
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Rhapsody (snapshots)
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Benefits
Quality:- Complements SD toolbox (finding NTF and STF), Cadences
NeoCircuit (transistor sizing) and NeoCell (layout generation)
- Produces SD topologies customized to performance specificrequirements
- less complex, better sensitivity to parameter variations, andlower power consumption
- Finds 6x-10x more constraint-satisfying solutions thanCircuitExplorer (Synopsis) and NeoCircuit (Cadence)
Effort:- Designs (including circuit sizing using NeoCircuit and layout using
NeoCell) can be ready much faster- Designers can focus on more challenging issues, like system
topology, selecting circuits
- Can be used by less-experienced designers
- Prototyping of new applications, e.g., reconfigurable SD ADC
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Application-specific modulator topologies
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Application-specific modulator topologies
The topology is an SFG containing integrators and
having all signal paths and coefficients of the signal
paths defined
A topology differs from another one in terms of
the type of the integrator
signal paths definition
numerical coefficients of the signal paths
For topology synthesis, they are the control
parameters and uniquely determine a topology
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Traditional modulator topologies
3rd order Delta-Sigma modulator topologies(a) Chain of Integrators with Feedforward Summation
(b) Chain of Integrators with Feedforward Summation and Local Feedback
(c) Chain of Integrators with Distributed Feedback
(d) Chain of Integrators with Distributed Feedback, DistributedFeedforward and Local Feedback
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Previous work: I
F. Medeiro, A. Verdu, A. Vazquez, Top-down Design of High
Performance Delta-Sigma Modulators, Kluwer, 1999
Designers have toselect anincompletetopology based onexperience
Coefficient design
is the only degreeof freedom to beexplored.
Set integrator types
Define signalpaths
Explore coefficientvalues
An incomplete
topology is defined
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Previous work: II
K. Francken, G. Gielen, A High-level Simulation and Synthesis
Environment for Delta-Sigma Modulators, IEEE Transactions on
Computer Aided Design of Integrated Circuits and Systems, Vol. 22,
No. 8, 2003, pp. 1049-1061.
Selected incomplete topologies(or complete topologies) are
stored in a library
Given design specifications, suchas SNR and DR, the tool selects
one with the smallest powerconsumption
Save and selectoptimal solution
Yes
No
Set integrator types
Define signal paths
Explore coefficientvalues
MeetSpecification?
Previous work: III
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Previous work: III
O. Bajdechi, G. Gielen, J. Huijsing, Systematic Design Exploration of
Delta-Sigma ADCs, IEEE Transactions on Circuits and Systems I, Vol.
51, No. 1, Jan 2004, pp. 86-95.
A filter level exploration of the design space
defined by abstract topology parameters
implemented using the
previous design flow
Subject to sensitivityanalysis for yield
possible designsolutions
Several best solutions in
terms of power consumption
A li ti ifi d l t t l i
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Application-specific modulator topologies
Y. Wei, H. Tang, A. Doboli, "DATE06: Systematic Methodology
for Designing Reconfigurable Delta Sigma Modulator
Topologies for Multimode Communication Systems", invited
paper, IEEE Transactions on CADICS, accepted for publication.
H. Tang, H. Zhang, A. Doboli, "Refinement based Synthesis of
Continuous-Time Analog Filters Through Successive DomainPruning, Plateau Search and Adaptive Sampling", IEEE
Transactions on CAD of Integrated Circuits and Systems, Vol.
25, No. 8, pp. 1421-1440, August 2006.
H. Tang, A. Doboli, "High-Level Synthesis of Delta-Sigma
Modulators Optimized for Complexity, Sensitivity and Power
Consumption", IEEE Transactions on CAD of Integrated
Circuits and Systems, Vol. 25, No. 3, pp. 597-607, March 2006.
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Proposed synthesis methodology
Define the solution space region with
all the possible modulator topologies
Formulate topology synthesis as an MINLP(Mixed-Integer Nonlinear Programming) problem
Formulate the design requirements as
symbolic cost functions and solve for the optimal solution
Advantages:
Global optimal solution is guaranteed
The methodology is scalable
The methodology could be fully automated
G i t l f 3rd d d l t
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Generic topology for 3rd order modulator
adderthetofromtscoefficiendfeedforwarandfeedback:addertheinput tofromtscoefficiendfeedforwar:
addertheoutput tofromtscoefficienfeedback:quantizertheinput to:
integratortheofoutputthe:
th
jji
th
i
th
i
th
i
iYtib
iaY
iY
G i t l g f 3rd d d l t
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Generic topology for 3rd order modulator
Chain of Integrators with Feedforward Summation
Generic topology for 3rd order modulator
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Generic topology for 3rd order modulator
Chain of Integrators with Distributed Feedback
Generic topology for 3rd order modulator
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Generic topology for 3rd order modulator
Chain of Integrators with Feedforward Summation and Local Feedback
Generic topology for 3rd order modulator
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Generic topology for 3rd order modulator
Chain of Integrators with Distributed Feedback,
Distributed Feedforward and
Local Feedback
Generic topology
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Generic topology
(1)1,...,1,0,0
1,...,1,,...,1,if,01,...,1,,...,1,if,0
+=
+==
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Symbolic TF for generic topology
Generalize the symbolic expressions for Delta-Sigma
modulator of any order
For example, the numerator and denominator
of of Delta-Sigma modulator of order are:
Solve the above equation using MATHEMATICA to
obtain and
dNTF
nNTF
N
)(
)(
zE
zV
NTF = )(
)(
zU
zV
STF =
N
NN
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=
=
+
+
+=
N
i
N
i
KNN
i
iiiiiiiiiiii
KK
KN
K
i
ii
K
N
K
K
N
K
n
ztttC
tCCNTF
K
KKKK
1 2
21212211)......)1(
...()1(
),...,,(),...,,(),...,,(
1
1
1
0
1
KNN
i
N
i
N
i
iiiiiiiiiiii
KK
KN
K
N
iii
K
N
K
N
K
N
N
j
N
j
N
jjjjjjjjjjjjj
N
ii
KK
KN
N
i
N
j
N
j
jNjjNji
K
N
N
i
Nii
K
N
K
N
i
N
i
N
i
iiiiiiiiiiii
KK
KN
KN
i
ii
K
N
N
K
K
N
K
d
ztttC
tCCatttaC
ttaCtaC
tttCtCC
NTF
K
KKKK
K
KKKK
K
KKKK
=
+
+ =
=
++
=
+
+
=
=
+
+
++
++++
+++
=
))......)1(
...()1()......
...()1(
...)......)1(...(()1(
1 2
21212211
1 2
21212211
1 2
2221
1 2
21212211
),...,,(),...,,(),...,,(
1
1
1
1
1),...,,(),...,,(),...,,(1
1
),1(),1(
2
2
1
1,
1
1
1
),...,,(),...,,(),...,,(
1
1
1
0
1
S b li NTF d STF
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Symbolic NTF and STF
Complexity of growth of terms is roughly 4N!
Generally, modulator order is kept below 6~8, thesymbolic expressions scale reasonably well
MINLP is able to handle large number of
constraints of different complexity
Symbolic expressions for other combination of
integrator types can be readily obtained viavariable substitution
MINLP problem formulation
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MINLP problem formulation
By equating the symbolic TF to the desired TF,3(N+1) equations are obtained with (N+1)(N+2)
unknowns
Properties for the symbolic TF:
All terms are nonlinear expressions of the defined
coefficient variables No quadratic terms
This mild nonlinear formulation is suitable to besolved by NLP
To select the signal paths, binary variables aredefined, so MINLP
MINLP formulation
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MINLP formulation
};1,0{),1(:
;0),(:
;0)(:
),(minimize
=
ii
ii
i
ii
wxsatisfyxtosubject
wxxhtosubject
xgtosubject
wxxf
Linear constraintsh
are added considering the complexityof nonlinear product term
Instead, we formulate h as:
smallveryiswhereotherwise,0andif1 == iii wxxwx
ii wxx
Topology exploration flow
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Topology exploration flow
Initialize modulator order
Initialize combination
Initialize OSR
Initialize MAG
Generate NTF
Generate and solveMINLP program
Meet SNR, DR specification
Save solution
Go to next combination
Optimal
solution
No
Yes
Yes
SNR, DR specification
Increaseorder
More combinations
IncreaseMAG
IncreaseOSR
YesYes YesYes
No No NoOSR in
range
Order
in range
MAG in
range
Minimumsensitivity test
Minimumpower test
Minimumpath test
Topology refinement
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opo ogy e e e t
Scaling => the voltage swings at the output of each
integrator are within a certain range
Nonideal blocks in Simulink
Experiment: 3rd order modulator
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p
3rd order Delta-Sigma modulator
DR>70db
The topology is able to achieve DR=72db andSNR=67db
5.1,32
,,5.1,3 max
==
===
MAGOSR
VUPN ref
)6629.0529.1)(6685.0(
)1994.1)(1(2
2
1+
+=
zzz
zzzNTF
Optimal topology
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A. Minimum signal path (topology not unique)
Optimal topology
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p p gy
B. Minimum sensitivity
Sensitivity cost function values are 1.723 and 2.250respectively, with all (good case)
L. Huelsman, Active and Passive Analog Filter Design, McGraw Hill, 1993
0.1, ji
j
i
q
x
P
x SS
Topology from Toolbox
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Topology from Toolbox
0.1, 334
3
3qt
q
a SSSensitivity cost function values is 4.454, with someterms larger than 1.0, e.g.
R. Schreier, The Delta-Sigma Toolbox 6.0,www.mathworks.com/matlabcentral/fileexchange, Nov 2003.
Triple-mode continuous-time modulator
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p
270kHz14.5/87EDGE190kHz15/90GSM
615kHz13/80CDMA2000
1.92MHz11.5/70UMTSBandwidthDR (bits/dB)Mode
Design
Specifications
484028, 325
6448404
9664483
--128962
GSM-EDGECDMA2000UMTS
OSR
OrderDesign
parameters
for possible
candidates
[1] R. Veldhoven, A Triple-Mode Continuous-Time Modulator With
Switched-Capacitor Feedback DAC for a GSM/EDGE/CDMA2000/UMTSReceiver, JSSC, Dec 2003.
Reconfigurable modulator topologies (1)
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0.5917m10.5316m20.5878m3
1.3013m2
1.3009m1
1.3944m3
V
0.0785m1
0.0442m2
0.0360m30.0013m3
0.0024m2
0.0069m1
0.3420m1
0.3605m2
0.4008m3
U
0.1970m1
0.1667m3
0.1670m2
0.7720m3
0.1552m2
0.1324m3
0.1364m1
0.6244m10.6585m2
0.7987m1
0.8988m2
0.8762m3
0.6274m1
0.5261m30.5133m2
0.4815m3
0.5159m1,
m2
0.4815m3
m20.5159m1,
0.1533m3
0.1467m2
0.1200m1
Topology opt1
Generated topologies
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U
0.0206m3
0.0342m1
0.0324m2
V
0.0349m1
1.3000m3
1.2080m2
0.4545m1
0.5556m2
0.5163m3
0.4545m1
m2,m3
0.2222m1
0.1829m3
0.1769m21.3000m2,m3
0.4500m1
0.4000m1
1.4765m10.5556m2
0.5163m3
1.3408m10.1545m1
0.8655m2
0.8000m3
0.4789m2
0.4771m3
0.5706m1
0.5143m2
0.6009m3
0.0941m2
0.0836m3
0.2647m1
0.0108m1
Topology opt2
Design complexity
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d : estimated design effortp : estimated power
consumption reduction
Np : # of signal paths
Np,r: # of non-reconfigurable cells
Nc,r : # of reconfigurable cells
SNR degradation due to circuit noise
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103
102
150
100
50
0
Frequency (f/fs)
Spectrum
(dB)
Output spectrum comparison
opt2, noise = 60dB[1], noise = 60dBopt2, noise = 70dB[1], noise = 70dB
opt2, ideal[1], ideal
40 35 30 25 20 15 10 5 010
0
10
20
30
40
50
60
70
80
90
Input amplitude [dB]
SNR[dB]
SNR comparison for different noise level
opt2, ideal[1], idealopt2, noise = 60dB[1], noise = 60dBopt2, noise = 50dB[1], noise = 50dB
Improvement as compared to the state-of-art design:
3dB for the case of -60dB noise level
5dB for the case of -50dB noise level
Experiments
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Experiments
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Compare the triple-mode modulator with three
single-mode modulators obtained with
toolbox
Design effort can be less than 1/3
Complexity can be as less as 40%
Power saving can be as large as 24.2%
More robust to circuit nonidealities
Experiments using PSoC
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Implementation of a reconfigurable Delta-Sigma
modulator using PSoC mixed-signal SoC
Experiments using PSoC
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Experiments using PSoC
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Experiments using PSoC
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Education & Training
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Hugo De Man, System-on-Chip Design: Impact on Education and
Research, IEEE Design & Test of Computers, July-Sept. 1999.
System architects/designers:
Cross-disciplinary background: EE/CE/CS
EE: signals, conversion techniques, impact of circuit
nonidealities, and know how to tackle these
CE: how HW & SW work together, abstraction levels,
successive refinement, trade-off analysis
CS: high-level description languages for systems, system and
circuit modeling techniques, formal verification
Education & Training
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Curricula, textbooks, projects, lab material, exercises?
A. Doboli and E. Currie
Embedded Mixed-Signal Systems: A DesignersPerspective, due to be published in 2007.
Conclusions
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PSoC: embedded mixed-signal architecture
Related research at Stony Brook
Systematic methodology for ADC design Automated circuit modeling
Education & training
Automated Macromodeling
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Produced macromodels:
Structural
No feedback dependencies (decoupled)
Symbolically characterized nonlinear current
sources
Extensible, accuracy is controllable
Insight into circuit
Reusable
Automated Macromodeling
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f(vin)vin vout
Black-box macromodel
Vin1
v3v2
Vin2
v1
VbnM5
M3 M4
M2M1
Circuit netlist Structural nonlinear macromodel
id3nk
k
id1nk
k
iCdb3nk
k
iCdb1nk
k
id4nk
k
id2nk
k
iCdb4nk
k
iCdb2nk
k
id3nk
k
id4nk
k
iCsb3nk
k
iCsb4nk
k
id1nk
k
iCdb5nk
k
(sCgd4gmg4)
vin2 v1
gms4 C3(sCgd2gmg2)
v2R3
(sCgd3gmg3)
vin1 v1
gms3 R2C2
V2
V3
C1 R1
V1
(sCgs3+gm3)
vin1
(sCgs4+gm4)
vin2
gmd3
v2,eq
gmd4
v3,eq
sCgd2
v3,eq
(R2,C2)
Automated Macromodeling
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v3
sCgd2
v3
d3nki
kd4nki
k
d5nki
k
d3nki
kd1nki
k
d4nki
kd2nki
k
v3
(sCgd3gmg3)
vin1
gms3
v1
C2 R2
v2
(sCgd4gmg4)vin2
gms4v1
(sCgd2gmg2)v2
C3 R3
v1
C1 R1
k
db5nkCC
ksb4nkC
ksb3nk
Ck
db3nk
Ck
db1nk
Ck
db2nk
Ck
db4nk
(sCgs3+gmg3)vin1
(sCgs4+gmg4)vin2
gmd3v2
gmd4
Vin1
v3v2
Vin2v1
VbnM5
M3 M4
M2M1
Circuit netlist
Automated Macromodeling
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103
104
105
106
107
108100
90
80
70
60
50
40
Frequency [Hz]
HD[d
B]
Comparison of HD2, HD3
HD3, SPICEHD3, modelHD2, SPICE
HD2, model
Comparison of HD2, HD3
Automated Macromodeling
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vout
Vin2
v3
RL CL
CfRf
v2
Vin1
v4
v1
M1 M2
M6
M8
M9M7M5
M3 M4
Vbn
Automated Macromodeling
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vout
d3nki
kd4nki
k
d5nki
kC
ksb3nk
Ck
sb4nk
Ck
db5nk
Ck
db3nk
Ck
sb2nk
Ck
sb1nk
d3nki
k
d1nki
k
v3
d2nk
ik d4nk
ik Ck db2nk Ck
db4nk
d8nki
kC
ksb8nk
Ck
db9nk
d9nki
k
d6nki
kd7nki
kC
kdb6nk
Ck
db7nk
gms3v1 (sCgd2)v3eq C2 R2(sCgd3gmg3)vin1
vin1 Vin2 C1 R1(sCgs3+gmg3) (sCgs4+gmg4) gmd3 gmd4
v2eq v3eq
v1
v2
(sCgd2gmg2)v2
(sCgd4gmg4)vin2 gms4v1
(s(Cf+Cgd8)(1/Rf))v4eq C3 R3
(sCgs8+gmg8)v4 C5 R5
+1/Rfgmg6)v3(sCgs8)v5eq
(s(Cgs6+Cf)
v4
C4 R4
Automated Macromodeling
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67/72
103
104
105
106
107
108
300
250
200
150
100
50
0 HD2 contribution
Frequency [Hz]
HD2
[dB]
M8M5M6
M3,4M1,2HD2, modelHD2, SPICE
Automated Macromodeling
8/2/2019 Mixed Signal Systems on Chip
68/72
vout
Vin2
v3
RL CL
CfRf
v2
Vin1
v4
v1
M1 M2
M6
M8
M9
M7M5
M3 M4
Vbn
Automated Macromodeling
8/2/2019 Mixed Signal Systems on Chip
69/72
103 104 105 106 107 108110
100
90
80
70
60
50
40
30
20
Frequency [Hz]
H
D[
dB]
HD3 comparison for twostage OpAmp
SPICEmodel
Automated Macromodeling
8/2/2019 Mixed Signal Systems on Chip
70/72
vo1
Ck db3nk
d7
nk
ikd3nk
ik Ck db7nk
Ck
db9nk
d11nki
kd9nki
kC
kdb11nk
d1nki
k
d3nki
k
d5nki
k
Ck
sb1nk
Ck
sb3nk
Ck
db5nk
Ck
db1nk
d13nki
kd1nki
kC
kdb13nk
v1
gms3
v1,eq(sCgd3gmg3)
vin1
sCgd9v3,eq R5 C5
sCgd1vo1,eq
(sCgd9gmg9)
v5
sCgs1v1,eq C3R3
(sCgs3+gmg3)vin1
(sCgs1+gm1)v3
gmd3v5 R1
gmd1vo1,eq C1
v3
(sCgd1gmg1) gms1v1 Ro1 Co1
v5
v3
M13
R
Vo1 Vo2
ClCl
v1 v2
v4v3
v6
Vin1 Vin2
M1 M2
M14
M3
M9
M11 M6 M12
M4
M8
M10
M7
v5
VbpVcmfb
Vbp
VbnM5
Automated Macromodeling
8/2/2019 Mixed Signal Systems on Chip
71/72
103 104 105 106 107 10890
80
70
60
50
40
30
20
10
0
Frequency [Hz]
HD[
dB]
HD3 comparison for OTA
HD3, SPICEHD3, model
Automated Macromodeling
8/2/2019 Mixed Signal Systems on Chip
72/72
1 2 3 4 5 6 7 8
0
5
10
15
20
25
30
35
40
45
50
Number of iteration
Error
[%]
complexity vs. accuracysinglestage, up to 100MHzsinglestage, up to 10MHztwostage, up to 100MHztwostage, up to 10MHz