Digital SemiconductorDigital Semiconductor

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MII For Gigabit EthernetMII For Gigabit Ethernet

Jacob TwerskyDigital Equipment Corporation (Digital)

IEEE 802.3z Task ForceSeptember 1996

Digital SemiconductorDigital Semiconductor

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ScopeScope

� Why Gigabit MII� MII in the layers model and the defined interface for

10/100 Mb/s (802.3u)� Gigabit MII proposal

Digital SemiconductorDigital Semiconductor

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ObjectivesObjectives

� Logical MII definition for Gigaethernet (no electrical andmechanical characteristics for now)

� Simple, inexpensive, easy-to-implement interconnectionbetween PHY and MAC

� As close as possible to the 10/100 MII definition� Allow half-duplex and full-duplex operation modes� Extendible

Digital SemiconductorDigital Semiconductor

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Why MII?Why MII?

� Two device - MAC and PHY - implementations– MAC and PHY technologies may be different– Vendors expertise

� System vendors can choose PHYs from different chipsuppliers (even for the same media)

� Makes differences among the various media absolutelytransparent to the MAC sublayer– Identical MAC devices may be used with any media– MAC sublayer definition in the standard is unified

Digital SemiconductorDigital Semiconductor

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MII Within the LAN Layers ModelMII Within the LAN Layers Model

OSI ReferenceModel Layers

LAN CSMA/CDLayers

higher layers

higher layers

LLC

MAC

Reconciliation

GigaBit MII

PHY

MDI

MEDIUM

PHYSICAL

DATA LINK

NETWORK

Digital SemiconductorDigital Semiconductor

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MII Signals in 802.3uMII Signals in 802.3u

RX_CLKRX_DVRXD<3:0>RX_ER

MDCMDIO

RECONCILIATION

PHY

StationManagement

TX_CLKTX_ENTXD<3:0>TX_ER

CRSCOL

Digital SemiconductorDigital Semiconductor

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MII Signals in 802.3zMII Signals in 802.3z

RX_CLKRX_DVRXD<7:0>RX_CTRL

MDCMDIO

RECONCILIATION

PHY

StationManagement

TX_CLKTX_ENTXD<7:0>TX_CTRL

CRSCOL

Oscillator125 MHz

Digital SemiconductorDigital Semiconductor

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Gigabit MII - Permissible Encoding inGigabit MII - Permissible Encoding inTransmitTransmit

TX_EN TX_CTRL TXD<7:0> Indication

0 0 00 through FFh Normal inter frame

0 1 5Xh Carrier extention

0 1 Otherwise Reserved

1 0 00 through FFh Normal data transmission

1 1 00 through FFh Transmit error propagation

Digital SemiconductorDigital Semiconductor

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Gigabit MII - Permissible Encoding inGigabit MII - Permissible Encoding inReceiveReceive

RX_DV RX_CTRL RXD<7:0> Indication

0 0 00 through FFh Normal inter frame

0 1 X0h Normal inter frame

0 1 Otherwise Reserved

1 0 00 through FFh Normal data reception

1 1 00 through FFh Data reception with errors

0 1 5Xh (X <> 0,Eh) Carrier extention

0 1 XEh False carrier indication

Digital SemiconductorDigital Semiconductor

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TX_CLK to TXD PathTX_CLK to TXD Path

� Assumptions (based on existing Fibre ChannelTransceivers):– TXD setup time to the rising edge of TX_CLK: 2 nS min– TXD hold time after rising edge of TX_CLK: 1.5 nS min– TX_CLK rise and fall time: 1 nS max

VALID DATA

tH

tSU

TX_CLK

TXD

Digital SemiconductorDigital Semiconductor

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TX_CLK to TXD Path DelaysTX_CLK to TXD Path Delays

1. Trace lines length2. Clock input pad3. Internal delay (data & clock)

4. Data output pad5. Package model (PQFP)6. PHY input capacitance

� Simulation done with Spice, Digital’s 0.5 micron CMOS process

Oscillator

PHY

MAC TX_CLK

TXD

12

3

4

5

6

Digital SemiconductorDigital Semiconductor

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TX_CLK to TXD - SimulationTX_CLK to TXD - Simulation

� Worst case for hold time– Trace lines length: 0.5 cm– Ideal clock (0 nS rise/fall time)– 3.465V, FF, 0– PHY input capacitance: 5pF

� Worst case for setup time– Trace lines length: 8 cm– Clock rise/fall time: 1 nS– 3.135V, SS, 100– PHY input capacitance: 5pF

o

C

C

o

Digital SemiconductorDigital Semiconductor

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Tx Gigabit MII and PCS codesTx Gigabit MII and PCS codesNo Carrier ExtentionNo Carrier Extention

TX_CLK

TX_EN

TXD<7:0>

CRS

TX_CTRL

P R E A M B L E

PCScodes

I I S D D D D D D D D D D D D T R I I I

Digital SemiconductorDigital Semiconductor

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Tx Gigabit MII and PCS codesTx Gigabit MII and PCS codes Carrier Extention Carrier Extention

TX_CLK

TX_EN

TXD<7:0>

CRS

TX_CTRL

P R E A M B L E 5X 5X 5X 5X

PCScodes

I I S D D D D D D D D D T R R R R R I I

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Rx Gigabit MII and PCS codesRx Gigabit MII and PCS codesNo Carrier ExtentionNo Carrier Extention

RX_CLK

RX_DV

RXD<7:0>

RX_CTRL

preamble sfd

PCScodes I I S D D D D D D D D D D D D T R I I I

CRS

Digital SemiconductorDigital Semiconductor

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Rx Gigabit MII and PCS codesRx Gigabit MII and PCS codes Carrier Extention Carrier Extention

RX_CLK

RX_DV

RXD<7:0>

RX_CTRL

preamble sfd 5X 5X 5X 5X

PCScodes

I S D D D D D D D D D T R R R R R I I

CRS

Digital SemiconductorDigital Semiconductor

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AdvantagesAdvantages

� Very close to the 10/100 MII definition– Based on a proven working scheme– Most of the definition can be taken directly from 802.3u

MII specification

� Allows control indication (CRS, COL) in parallel with thedata

� Enables further extendibility� Enables simple 10/100/1000 MAC implementations

Digital SemiconductorDigital Semiconductor

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SummarySummary

� This presentation proposes:– A set of interface signals for Gigabit MII which are as

close as possible to the 10/100 MII definition– Code for dealing with carrier extention