Post on 05-Jan-2016
LOW VOLTAGE OP AMPS• We will cover:
– Low voltage input stages– Low voltage bias circuits– Low voltage op amps– Examples
• Methodology:– Modify standard circuit blocks for reduced
power supply voltage– Explore new circuits suitable for low voltage
design
ITRS Projection – near term
ITRS Projection – longer term
Low-Voltage, Strong-Inversion Operation
• Reduced power supply means decreased dynamic range• Nonlinearity will increase because the transistor is
working close to VDS(sat)
• Large values of λ because the transistor is working close to VDS(sat)
• Increased drain-bulk and source-bulk capacitances because they are less reverse biased.
• Large values of currents and W/L ratios to get high transconductance
• Small values of currents and large values of W/L will give smallVDS(sat)
• Severely reduced input common mode range• Switches will require charge pumps
Input common mode range drop
VDD – VDS3sat + VT1 > vicm > VDS5sat + VT1 + Von1
1.25 -0.25 + 0.75 > vicm > 0.25+0.75+0.25, unsymmetric!
p-n complementary input pairs
n-channel: vicm > VDSN5sat + VTN1 + VonN1
p-channel: vicm <VDD- VDSP5sat - VTP1 - VonP1
Non-constant input gm
N
constant input gm solutionLet Vb1 depends on Vicm so that Mb1 is turned on when MN1,2 are turned off, and Ip becomes 4 times.
Similarly when MP1,2 are off, In becomes 4 times.
When both pair on, In and Ip are bothe 1 times
Set VB1 = Vonn and VB2 = Vonp
Rail-to-rail constant gm input
As Vin+ and Vin- reduce, MN1,2 begins to turn off, MNC1,2 also begins to turn off. I7 reduces, so does I8. I9 = I12-I8 increases, so does I10, which is 3(I12-I8)=3(Ip-In), which becomes 3Ip when n-pair turns off.
When both on, I5=I1=I12=IBP=Ip; I11=I7=I6=IBN=In
Vi+ Vi-
Complementary input stage with rail-to-rail Vicmr and constant gm
Vi+ Vi-
3:
:3
Vi- Vi+
Ip
In
3(Ip-In)
Ip
In
InVbp
Vbn
Ip
3(In-Ip)
In
Ip
(Ip-In)
(In-Ip)
in+
in-
ip+
ip-
N1 N2P1 P2PC1,2 NC1,2
BN
BP
1 2 3 4
Vo1+ Vo1-
Folded cascode stage: summing current and convert to voltage
in+
in-
ip+
ip-
-in+
-ip-
io1-=ip- - in+
in+ =+gmn1*vid/2
in- = -gmn1*vid/2
ip+ =+gmp1*vid/2
ip- = -gmp1*vid/2
io1- =ip- - in+ = -(gmp1+gmn1)*vid/2
io1+=ip+ - in- = (gmp1+gmn1)*vid/2
Vo1- = io1- /go1
Vo1+ = io1+ /go1
Vo1d = (Vo1+ -Vo1+ ) = vid *(gmp1+gmn1)/go1
Vxx
Vyy
Vzz
Vbb
Folded cascode stage: feedback to reduce go1
Vxx
Vyy
Vzz
M1 M1
M2a M2a M2bM2b
Vbb
M3 M3
M4M4
i
gmn1vd/2 gdsn1
gds4
gds3
vcp
vcn
gds1
gds2agds2b
gm2avcn
+gmb2avcn
gm2bvcn
+gm2bvcp
+gmb2bvcn
vo1+
gm3vcp
Show that it is possible to make gain (vo1/vd) infinity by proper sizing.
Folded cascode stage: feedback to reduce go1, alternative
Vxx
Vyy
VzzM1a M1a
M2 M2
M1bM1b
Vbb
M3 M3
M4M4
i
gmn1vd/2 gdsn1
gds4
gds3
vcp
vcn
gds1
gds2a
gds2b
gm2avcn
+gmb2avcn
gm2bvcp
vo1+
gm3vcp
In either case, you can set vd=0, write KCL’s for the vn, vn and vo1 nodes, eliminate vn and vp, obtain expression in vo1 alone, set coefficient to zero, this gives conditions for go=0. From that, you can solve for gm for the feedback transistor and see how that can be realized.
For example, in the first choice, if you make gds of M1 and M3 4 times as large as the other transistors, it becomes relatively simpler to meet the conditions.
Small signal analysis for 2nd choice is easier, but quiescent voltage a concern. You can also feedback to PMOS transistors.
Feeding back to top or bottom transistors faces big challenges when supply voltage increases.
If the whole M2 (or M3 in the P version) is controlled by feedback, then the VgsQ of M2 is independent of supply.
M1
VG3
VG2
M1
M3
M2
M4
M3
M2
M4
Regulated Cascode for gain improvement
Vxx
Vzz
k
VD
VS
VS
VD
VG
VG
If you regulate, you have to regulate all four.
Second stage
Vxx
Vyy
VzzM1 M1
M2 M2
M6M6
Vbb
M3 M3
M4M4M7 M7
Second stage push pull: Monticelli style
Vxx
Vyy
VzzM1 M1
M2 M2
M6M6
Vbb
M3 M3
M4M4M7 M7
Requires: VDD-VSS > Vgs6+Vgs7+Vdssat_floating_CS
Vbp Vbn
D. M. Monticelli, “A quad CMOS single-supply Op Amp with rail-to-rail output swing,” IEEE J.Solid-State Circuits, no. 6, pp. 1026–34, Dec. 1986.
Don’t doVxx
Vyy
VzzM1 M1
M2 M2
M6M6
Vbb
M3 M3
M4M4M7 M7
Unpredictable current in second stage
Vzz
Vbn Vxx
Vbp
So, Vg6Q = VzzThis sets Id6.Q So, Vg7Q = Vxx
This sets Id7Q.
These circuits can come from the same biasing circuit for the main amplifier.So, no extra current, power consumption, noise, and offset introduced.
gds4
gds3
gds1
gds2a
gm2avcn
+gmb2avcn
vo1+
gm3vcp
Floating CS do not change ro1 or DC gain
gdsn gdsp
gmnvo1+
-gmpv’o1+
V’o1+
The impedance looking down from Vo1+ is Rn
To find impedance looking up from Vo1+, inject a test current i up.
V’o1+ = i*Rp
i_gdsn/p = (i-gmnvo1++gmpv’o1+)
Vo1+=V’o1+ + i_gdsn/p /(gdsn + gdsp)
Vo1+=i*Rp+(i-gmnvo1++gmpi*Rp) /(gdsn+gdsp)
Vo1+(1+gmn /(gdsn+gdsp))=i*{Rp[1+gmp/(gdsn+gdsp)] +1/(gdsn+gdsp)}
Vo1+/I =Rp gmp/gmn
Rn
Rp
So, size them so that gmp ≈ gmn
Note: gmn and gmp include possible body effects.
To the two gate terminals of M6 and M7, the two floating CS appears as a voltage source providing a voltage offset between the gates.
The impedance seen by the two gate terminals can be calculated by:
Rs = (Vgp – Vgn)/(current through the floating CS) = (Vgp – Vgn)/(gmp*Vgp – gmn*Vgn + (Vgp – Vgn)*(gdsn+gdsp)) ≈ 1/(gmp + gdsn+gdsp) ≈ 1/gmp
The above assumed that the NMOS and PMOS are sized to have the same gm.
Also, the calculation is only valid when both NMOS and PMOS are fully on and both in saturation.
When Vo is experiencing large swings, these conditions are not met. And the voltage difference between the two gate terminals no longer remain constant.
Differential signal path compensation
Vxx
Vyy
VzzM1 M1
M2 M2
M6M6
Vbb
M3 M3
M4M4M7 M7
In order for M6 and M7 to have well defined quiescent current, we have to bias the circuit so that at Q, Vd2 = Vzz.
This is naturally provided by the usual bias generator:
Vzz
Vbb
Problem:Vd2 is a high impedance
node, small current mismatch in M1 and M4 leads to significant voltage change at vd2, which in turn changes the biasing current in the output stage.
Solution:use feedback to stabilize
common mode of Vd2.
VzzVd2L Vd2R
Feedback toM4 or part of it
Since Vd2L and Vd2R are normally nearly constant. We do not need to worry about the input range accommodation for this circuit.
Size the circuit so that, when vid =0, Id6 remain near desired level over all process variations in M1 and M4.
Current sensors
Quiescent biasing
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 10, OCTOBER 1998
Vo+ and Vo- also need common mode stabilization
M6M6
M7 M7
Vocmd
M7t M7t
M7t’s are in triode
Choose R to a couple times bigger than RoChoose C to be near or a couple times larger than Cgs of CMFB circuit.
R R
C C
M6M6
M7 M7Vocmd
M7t M7t
M7t’s are in triode
R R
C C
Insert these
Why RC in common mode detector
V1
V2
R
R
Cgs
V
KCL at V:
(V1 – V)/R + (V2 – V)/R = V * sCgs
(V1 + V2)/R = V(sCgs + 2/R)
V = (V1 + V2)/2 * 1/(1 + sRCgs/2)
When |s| =|jw| << 2/RCgs,
V ≈ (V1 + V2)/2
Otherwise V is not close to common mode
To have CM detector work up to GB,
R << 2/(2GB*Cgs)
Why RC in common mode detector
V1
V2
R
R
Cgs
V
KCL at V:
(V1 – V)(1/R +sC) + (V2 – V) (1/R +sC) = V * sCgs
(V1 + V2) (1/R +sC) = V(sCgs + 2/R +2sC)
V = (V1 + V2)/2 * (1 + sRC)/(1 + sRC + sRCgs/2)
As long as Cgs/2 < C, at all freq:
V ≈ (V1 + V2)/2
C
C
Hence, the RC network acts as a better CM detector
Why CMBF to M7t instead of first stage:
Vo1+
Vo1-Vo+
For CM behavior, assume DM=0.Vo1+=Vo1-, and Vo+=Vo-=Vocm.
Without CMFB effect, at Q, Vo+ will be equal to Vg, which may be far below desired Vocm level.
With CMFB connected, the feedback effect will drive Vo1 so as to move Vo+ up to the desired Vocm level.
Since Vo1+ and Vo1- have a competing action on Vo+, it may take quite bit Vo1 movement to achieve the desired Vo+ movement, causing the biasing current in the second stage to be much larger than what is intended.
Vg
Compensation for diff signal path closed-loop stability
Vxx
Vyy
VzzM1 M1
M2 M2
M6M6
Vbb
M3 M3
M4M4M7 M7
CCCC
At relatively low frequency:
• Because of gain from Vo1 to Vo, small signal Vo1 is much smaller than small signal Vo.
• Small signal current in compensation network is approximately Vo/(1/gmz+1/sCc).
• This current is injected to the Vo1 node.
Alternatively, a similar current can be injected:
• Impedance looking into a cascode node is about 1/gm
• Connecting Cc to a cascode node generates a current of the form Vo/(1/gm +1/sCc)
• Because the base transistor is a current source, this small signal current goes to the Vo1 node
• Even at high frequency, the current form is still valid.
Alternative compensation
Vxx
Vyy
VzzM1 M1
M2 M2
M6M6
Vbb
M3 M3
M4M4M7 M7
CCCC
In the Cc+Mz connection,
• Bias voltage of Mz can be matched to track bias voltage of M6 robustness to process and temperature variations
• Size of Mz can be parameter scanned so as to place zero to cancel the secondary pole of the amplifier
In the Cc to cascode connection,
• Bias voltage can still be derived using current mirrors from a single current source, still have process and temperature tracking
• But size of cascode transistor is determined based on folded cascode stage design
• Cannot arbitrarily choose its size without considerations for output impedance at Vo1, gain of op amp, and so on.
Alternative compensation
Vxx
Vyy
VzzM1 M1
M2 M2
M6M6
Vbb
M3 M3
M4M4M7 M7
CCCC
VicmVicm
Vo+, Vo-
Use open loop Vicm sweep to find a “sweet spot” for your Vicm
VicmVin
Vo+
With Vicm at “sweet spot”, sweep Vin near Vicm with very fine steps (uV)
Vin
Vo-
d(Vo+-Vo-)dVin
Vo+-Vo- Vin
Vb2
VCMFB
Vb1
CC
Vo+
Vo-
Vo+
Vo-
Folded cascode stage: summing current and convert to voltage
Vi-
3:1
Summing circuit to add n-signal and p-signal together
Rail-to-rail constant gm input
Coban and Allen, 1995
The composite transistor
Bulk-Driven MOSFET
Bulk-Driven, n-channel Differential Amplifier
I1=I2=I5/2As Vic varies, Vd5 changes
and gmb varies
Varied gain, slew rate,
gain bandwidth;
nonlinearity; and difficulty
in compensatio
n
Bulk-driven current mirrors
Increased vin range and vout range
Traditional techniques for wide input and output voltage swings
1
Io =Iin+Ib
Iin
Ib Ib
1 1
1
1/4
VT+Von
VT+2Von
VonVon
>2Von
+
–VT+Von
Traditional techniques for wide input and output voltage swings
1
Io
Iin Ib Ib
1
1
1/4
VT+Von
VT+2Von
VonVon
>2Von
+
–Veb
Io =Iin
A 1-Volt, Two-Stage Op Amp
Uses a bulk-driven differential input pair, wide swing current mirror load, and emitter follower level shifter
Op AmpPerformance
Frequency Response
Low voltage VBE and PTAT reference
Threshold Voltage Tuning for low power supply voltages operation
+-
+ -
dcntntn VVV '
dcptptp VVV '
dcnV tnV
dcpV tpV
virtualtransistors
standardtransistors
Implementation of the voltage sources+-
+ -
1 12
21 1
2
Bias Voltage
21
C
2C
IN OUT
dcV
Bias Voltagedc
V
IN OUT1C
2C
A low voltage Op Amp core
Op Amp Implementation
Clock booster Bias voltage generator
VDD
OUT
VSS
RVDD
IN
OUTM1
M2
M3
M4
M5
C -+
Clock booster (doubler)
CB1 >> CBL
Experimental Results
Power supply 750mV
Slew Rate 3.1V/uS
GB 3.2MHz
DC gain 62dB
Input offset voltage 2.2mV
Input common mode range 0.1V-0.58V
Output swing for linear operation 0.31V-0.58V
PSRR at DC 82dB
CMRR at DC 56dB
Total power consumption 38.3uW
Common mode feedback for low voltage
1.5v op amp for 13bit 60 MHz ADC
Output Stage and CMFB
Folded cascode with AB output
Lotfi 2002
Simulated performance• 0.25 um process
• 1.5 V power supply
• 82 dB DC gain
• 2 V p-p diff output swing
• 170 MHz UGF @ 10 pF load
• 77o PM with = 1/5
• 0.02% 1V step settling time: 8.5 ns
• Full output swing Op Amp power: 25 mW
Differential difference input AB output
Alzaher 2002
Nested Miller Cap Amplifier
Not much successes
Low voltage amp
Low voltage amp
LOW POWER OP AMPS• Op Amp Power = (VDD-VSS)*Ibias
– Reduce supply voltage: effect is small• Many challenges in low voltage design same as
before
– Reduce bias: factor of hundred reduction• Weak inversion operation• Nano-amp to small micro-amp currents• Needs small current biasing circuits and small
current reference generators• Needs output stage to drive the load
– Design it so that it consume tiny quiescent power– But generate sufficient current for large signals
– Tradeoff speed for reduced power
Sub-threshold OperationMost micro-power op amps use transistors in the sub-threshold region.
np~1.5; nn~2.5
Two-Stage, Miller Op Amp in Weak Inversion
At VDD-VSS=3V, ID5=0.2uA, ID7=0.5uA, got A=92dB, GB=50KHz, P=2.1uW
Push-Pull Output in Weak InversionFirst stage gain
Total gain
S=W/L
Increasing gain
go
Gain=gm/go
What is VON?
L5=L12, W12=W5/2S13<<S4
Increasing Iout with positive feedbackWhen vi1>vi2
i2>i1
i26=i2-i1>0i27=0
i28=A*i26
itail=I5+i28
=i1+i2
i2/i1=e(vi1-vi2)/nvt
=evin/nvti2=i1evin/nvt
I5+ A*(evin/nvt-1)i1= (evin/nvt+1)i1
i1=I5 /{A+1-(A-1)evin/nvt)}
A=0 is normal case
A > 0 can greatly enhance available
output current for load driving
A=0
A=1
A=2
A=3
i1
i2
i1=i2
i2=i1evin/nvt
as vin
I5
I5
i1+i2=I5
New i1+i2
i1+i2 much faster than i2-i1
DC Offset (Self-mixing)
AD
ADc 0
c
)(, tx RFoffset