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III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 1
ECE2072/TRC2300/TEC2172 Digital Systems:Implementations of two-level logic
(Sec3.2.3 Katz2e) based on textbook
Contemporary Logic Design, 2nd Editionby R. H. Katz and G. Borriello
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III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 2
Implementations of two-level logic (Sec3.2.3)
Sum-of-productsAND gates to form product terms (minterms)OR gate to form sum
Product-of-sumsOR gates to form sum terms (maxterms)AND gates to form product
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 3
Two-level logic using NAND and NOR gates
NAND-NAND and NOR-NOR networksde Morgan’s law: (A + B)’ = A’ • B’ (A • B)’ = A’ + B’written differently: A + B = (A’ • B’)’ (A • B) = (A’ + B’)’
In other words ––OR is the same as NAND with complemented inputsAND is the same as NOR with complemented inputsNAND is the same as OR with complemented inputsNOR is the same as AND with complemented inputs
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 4
Two-level logic using NAND gates
Replace minterm AND gates with NAND gatesPlace compensating inversion at inputs of OR gate
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 5
Two-level logic using NAND gates (cont’d)
OR gate with inverted inputs is a NAND gatede Morgan’s: A’ + B’ = (A • B)’
Two-level NAND-NAND networkinverted inputs are not countedin a typical circuit, inversion is done once and signal distributed
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 6
Two-level logic using NOR gates
Replace maxterm OR gates with NOR gatesPlace compensating inversion at inputs of AND gate
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 7
Two-level logic using NOR gates (cont’d)
AND gate with inverted inputs is a NOR gatede Morgan’s: A’ • B’ = (A + B)’
Two-level NOR-NOR networkinverted inputs are not countedin a typical circuit, inversion is done once and signal distributed
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 8
A
B
C
D
Z
A
B
C
D
Z
NAND
NAND
NAND
Conversion between forms
Convert from networks of ANDs and ORs to networks of NANDs and NORs
introduce appropriate inversions ("bubbles")Each introduced "bubble" must be matched by a corresponding "bubble"
conservation of inversionsdo not alter logic function
Example: AND/OR to NAND/NAND
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 9
Z = [ (A • B)’ • (C • D)’ ]’
= [ (A’ + B’) • (C’ + D’) ]’
= [ (A’ + B’)’ + (C’ + D’)’ ]
= (A • B) + (C • D)
Conversion between forms (cont’d)
Example: verify equivalence of two forms
A
B
C
D
Z
A
B
C
D
Z
NAND
NAND
NAND
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 10
Step 2conserve"bubbles"
Step 1conserve"bubbles"
NOR
NOR
NOR
\A
\B
\C
\D
Z
NOR
NORA
B
C
D
Z
Conversion between forms (cont’d)
Example: map AND/OR network to NOR/NOR networkA
B
C
D
Z
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 11
Z = { [ (A’ + B’)’ + (C’ + D’)’ ]’ }’
= { (A’ + B’) • (C’ + D’) }’
= (A’ + B’)’ + (C’ + D’)’
= (A • B) + (C • D)
Conversion between forms (cont’d)
Example: verify equivalence of two forms
A
B
C
D
Z
NOR
NOR
NOR
\A
\B
\C
\D
Z
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 12
Multi-Level Logic: Advantages (Sec3.3 Katz 2e)Reduced sum of products form:
x = A D F + A E F + B D F + B E F + C D F + C E F + G
6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!)25 wires (19 literals plus 6 internal wires)
1
2
3
4
5
6
7
1
2 3 4
A
A
A
B
B
B
C
C
C
D
D
D
D
E
E
E
E
F
F
F
F
F
F
F
G
G
x x
Factored form:x = (A D + A E + B D + B E + C D + C E) F + G
= (A (D + E) + B (D + E) + C( D + E) ) F + G= (A + B + C) (D + E) F + G
1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate10 wires (7 literals plus 3 internal wires)
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 13
Multi-Level Logic: SimplificationMulti-Level Optimization:
1. Factor out common sublogic (reduce fan-in, increase gate levels),subject to timing constraints
2. Map factored form onto library of gates
3. Minimize number of literals (correlates with number of wires)Factored Form:
sum of products of sum of products . . .
X = (A B + B' C) (C + D (E + A C')) + (D + E)(F G)
A
B B
C C D
E
A
C
F
G D
E
F 1
F 2
F 5 F 4
F 3
X
+
+
+
+ +
•
• • •
•
• •
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 14
Multi-Level Logic: Simplification contd.Operations on Factored Forms:
• Factoring
• Decomposition
• Extraction
• Substitution
• Collapsing
Manipulate network by interactivelyissuing the appropriate instructions
There exists no algorithm that guarantees"optimal" multi-level network will be obtained
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 15
Multi-Level Logic: Simplification contd.Factoring: expression in two level form re-expressed in multi-level form
F = A C + A D + B C + B D + E
can be rewritten as:
F = (A + B) (C + D) + E
(9 literals)
(5 literals)
Before Factoring After Factoring
AA
A
B
B
BCC
C
D
D
D
E
E
FF
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 16
Multi-Level Logic: Simplification contd.Decomposition:
Take a single Boolean expression and replace with collection of newexpressions:
F = A B C + A B D + A' C' D' + B' C' D'
F rewritten as:
F = X Y + X' Y'X = A BY = C + D
(12 literals)
(4 literals)
Before Decomposition
FA
A
A
B
B
B
C
C
C
D
D
D
After Decomposition
F
AB
CD
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 17
Multi-Level Logic: Simplification contd.Extraction: common intermediate subfunctions are factored out
F = (A + B) C D + EG = (A + B) E'H = C D E
can be re-written as:
F = X Y + EG = X E'H = Y EX = A + BY = C D
11 literals, 8 gates
11 literals, 7 gates
"Kernels": primary divisors
Before Extraction After Extraction
X
E
E
E
GG
Y
HH
A
A
A B
B
BC
C
C D
D
D
FF
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 18
Multi-Level Logic: Simplification contd.Substitution: function G into function F, express F in terms of G
F = A + B C DG = A + B C
F rewritten in terms of G:
F = G (A + D)
Collapsing: reverse of substitution; use to eliminate levels to meettiming constraints
F = G (A + D)= (A + BC) (A + D)= A + B C D
(4 literals for F)
(3 literals for F)
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 19
Multi-Level Logic: Simplification contd.Key to implementing these operations: "division" over Boolean functions
F = P Q + R
divisor quotient remainder
example:X = A C + A D + B C + B D + EY = A + B
X "divided" by Y is—X = Y (C + D) + E
Complexity: finding suitable divisorsF = A D + B C D + EG = A + B
G does not divide F under algebraic division rulesG does divide F under Boolean rules (very large number of these!)
F/G = (A + C) D F = [G (A + C) D] + E= (A + B) (A + C) D + E= (A A + A C + A B + B C) D + E= (A + B C) D + E= A D + B C D + E ¦
F written as G Q + R
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 20
Level 1 Level 2 Level 3 Level 4
originalAND-OR network
A
CD
B
B\C
F
introduction andconservation of
bubbles A
CD
B
B\C
F
redrawn in termsof conventional
NAND gates A
CD
\B
B\C
F
F = A (B + C D) + B C’
Conversion of multi-level logic to NAND gates(Sec3.4.2 Katz 2e)
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 21
Level 1 Level 2 Level 3 Level 4
A
CD
B
B\C
ForiginalAND-OR network
introduction andconservation of
bubbles A
C
DB
B
\C
F
redrawn in termsof conventional
NOR gates\A
\C\D
B
\BC
F
Conversion of multi-level logic to NORs
F = A (B + C D) + B C’
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 22
Conversion between forms
Example
A
XBCD
F
original circuit
A
XBCD
F
add double bubbles to invert all inputs of OR gate
\D
A
BC
F
\D
A
X
BC
F\X
insert inverters to eliminate double bubbles on a wire
add double bubbles to invert output of AND gate
X
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 23
Summary for multi-level logic
Key design approachIdentify common Boolean subexpressions across logic functionsShare subexpressions among multiple functions to reduce literals
Advantagescircuits may be smallergates have smaller fan-incircuits may be faster
Disadvantagesmore difficult to designtools for optimization are not as good as for two-levelanalysis is more complex
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 24
Time behavior of combinational networks (Sec3.5 Katz2e)
Waveformsvisualization of values carried on signal wires over timeuseful in explaining sequences of events (changes in value)
Simulation tools are used to create these waveformsinput to the simulator includes gates and their connectionsinput stimulus, that is, input signal waveforms
Some termsgate delay — time for change at input to cause change at output
min delay – typical/nominal delay – max delaycareful designers design for the worst case
rise time — time for output to transition from low to high voltagefall time — time for output to transition from high to low voltagepulse width — time that an output stays high or stays low between changes
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 25
F is not always 0pulse 3 gate-delays wide
D remains high forthree gate delays after
A changes from low to high
FA B C D
Momentary changes in outputs (Sec3.5.2 Katz2e)
Can be useful — pulse shaping circuitsCan be a problem — incorrect circuit operation (glitches/hazards)Example: pulse shaping circuit
A’ • A = 0delays matter
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 26
initially undefined
close switch
open switch
+
open switch
resistorA B
CD
Oscillatory behavior (Sec3.5.3 Katz2e)
Another pulse shaping circuit
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 27
Hazards & Glitches (Sec3.5.4 Katz2e)Hazards/Glitches and How to Avoid Them
Unwanting switching at the outputs
Occur because delay paths through the circuit experiencedifferent propagation delays
Danger if logic "makes a decision" while output is unstableOR hazard output controls an asynchronous input (theserespond immediately to changes rather than waiting for asynchronizing signal called a clock)
Usual solutions:• wait until signals are stable (by using a clock & SYNCHRONOUS
TIMING METHODOLOGY)
• never, never, never use circuits with asynchronous control inputs
• design hazard-free circuits
Suggest that first two approaches be used, but we'll tell you abouthazard-free design anyway!
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 28
Hazards & Glitches contd.Hazards/Glitches and How to Avoid Them
Kinds of Hazards
Static 0-hazard
Dynamic hazards
Static 1-hazard
1
Input change causes output to go from 1 to 0 to 1
Input change causes output to go from 0 to 1 to 0
Input change causes a double changefrom 0 to 1 to 0 to 1 ORfrom 1 to 0 to 1 to 0
1
0
1
0 0
1
0 0
1
1 1
0 0
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 29
Hazard Detection & Elimination in 2-Level Networks (Sec3.5.5 Katz2e)
Glitch Example (SoP form)
F = A' D + A C'input change within product term
input change that spans product termsmay cause output to change from 1 to 0 to 1
G1
G2
G3
A\C
\AD
F
G1
G2
G3
A\C
\AD
F
1
1
11
0
0
0
1
1
11
0
0
0
ABCD = 1100 ABCD = 1101
G1
G2
G3
A\C
\AD
F
G1
G2
G3
A\C
\AD
F
0
1
00
1
0
0
1
1
11
1
0
0
ABCD = 1101 ABCD = 0101 (A is still 0)
G1
G2
G3
A\C
\AD
F
0
1
01
1
1
1
ABCD = 0101 (A is 1)
A AB
00 01 11 10
0 0 1 1
1 1 1 1
1 1 0 0
0 0 0 0
00
01
11
10 C
CD
D
B
1
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 30
Hazard Detection & Elimination in 2-Level Networks contd.
Glitch ExampleGeneral Strategy: add redundant terms to cover all singe bit inputtransitions
F = A' D + A C' becomes A' D + A C' + C' D
This eliminates 1-hazard. 0-hazard are not possible with SoP since no product switchingtakes place
A AB
00 01 11 10
0 0 1 1
1 1 1 1
1 1 0 0
0 0 0 0
00
01
11
10 C
CD
D
B
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 31
Consider now F in PoS form:
F = (A' + C')(A + D)
A AB 00 01 11 10
0 0 1 1
1 1 1 1
1 1 0 0
0 0 0 0
00
01
11
10 C
CD
D
B
Hazard Detection & Elimination in 2-Level Networks contd.
Glitch Example
Glitch present!
Add term: (C' + D)
Note: 1-hazards not possible withPoS form!
This expression is equivalentto the hazard-free SoP form of F
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 32
Dynamic Hazards: (Sec3.5.8 Katz2e)Example with Dynamic Hazard
Three different paths from B or B' to outputABC = 000, F = 1 to ABC = 010, F = 0
different delays along the paths: G1 slow, G4 very slow
Handling dynamic hazards very complex
Beyond our scope
G1
G2
G3
G5
G4
\A B
\B
\B \C F
A
0 1
1
1 0
1
0 1
1 0
1 0 1
1 0 0
1 0
1 0 1 0
Slow
V ery slow
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 33
Implementations Summary• Transition from Simple Gates to more complex gate building blocks
• Conversion from AND/OR, OR/AND to NAND/NAND, NOR/NOR
• Multi-Level Logic: Reduced gate count, fan-ins, but increased delay
• Time Response in Combinational Logic:
Gate Delay, Rise Time, Fall TimeHazards and Hazard-free Design
III - Working with Combinational Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 34
Working with combinational logic summary
Design problemsfilling in truth tablesincompletely specified functionssimplifying two-level logic
Realizing two-level logicNAND and NOR networksnetworks of Boolean functions and their time behavior
Time behaviorLater
combinational logic technologiesmore design case studies