Lecture 18

CMOS Inverter (II)

1

CMOS inverter

2

Polysilicon

In Out

VDD

GND

PMOS

Metal 1

NMOS

OutIn

VDD

PMOS

NMOS

N Well

3

Characteristics of CMOS inverter

Nucleus of all digital designs.

Robustness: static behavior

Speed performance：dynamic behavior

Reliability：power consumption

Economy：area, complexity

Static Behavior Function

Robustness

Technology uncertainty: affects the threshold voltage and the

saturation current

Noise（crosstalk of coupled interconnects, simultaneous

switching noise (SSN)）

4

5

CMOS dynamic behavior

V outV out

R n

R p

V DDV DD

CLCL

V out from 0 to 1V out from 1 to 0

CMOS Inverter

Static Behavior

6

7

Dc property of CMOS inverter

VDD VDD

Vin ＝VDD Vin ＝0

Vout

Vout

Rn

Rp

There is no direct way

from power to ground

when CMOS inverter is

static if the leakage

current is ignored. Hence,

there is no static power

consumption. It is the

reason why CMOS takes

place of NMOS.

8

I-V characteristic of CMOS inverter

PMOS

VDSp

IDp

VGSp=-2.5

VGSp=-1VDSp

IDn

Vin=0

Vin=1.5

Vout

IDn

Vin=0

Vin=1.5

Vin = VDD+VGSpIDn = - IDp

Vout = VDD+VDSp

V in = V DD +V GSp

IDn = - IDp

V out = VDD

+V DSp

9

IDn

Vout

Vin = 2.5

Vin = 2

Vin = 1.5

Vin = 0

Vin = 0.5

Vin = 1

NMOS

Vin = 0

Vin = 0.5

Vin = 1Vin = 1.5

Vin = 2

Vin = 2.5

Vin = 1Vin = 1.5

PMOS

I-V characteristics of CMOS inverter

10

Vout

Vin0.5 1 1.5 2 2.5

0.5

11

.52

2.5

NMOS resPMOS off

NMOS satPMOS sat

NMOS offPMOS res

NMOS satPMOS res

NMOS resPMOS sat

Transfer Characteristics of CMOS inverter

VIL VIH

VOL

VOH

VTN |VTP|

Noise margin NML=VIL-VOL

NMH=VOH-VIH

11

0

1

VIL

VIH

VOL

VOH

Undefined

region

The wider the noise margin is，the better

the noise immunity performance is.

Calculation of noise margin

12

VOH

VOL

Vin

Vout

VM

VIL VIH

OH OL DD

IH IL

V V VV V

g g

M

IH M

VV V

g DD M

IL M

V VV V

g

H DD IHNM V V L ILNM V

CMOS small signal model

13

Vgs

G

S

D

gmnvgs

ron

gmpvgs

rop

)0(

|)|(

op

TpinDDpm p

r

VVVkg

PMOS saturated

1

DD

( )

[ ( | |]

mp p DD out

op p in Tp

g k V V

r k V V V

PMOS linear

)0(

)(

on

Tninnm n

r

VVkg

NMOS saturated

1

in[ ( )]

mn n out

on n Tn

g k V

r k V V

NMOS linear

14

2

2

linear region2

/ 2 1 saturation region

out

n in Tn out

DN

n in Tn out

Vk V V V

I

k V V V

2

2

( )( ) linear region

2

/ 2 1 ( ) saturation region

DD out

p DD in Tp DD out

DP

p DD in Tp DD out

V Vk V V V V V

I

k V V V V V

2

'

2

DS

D n GS T DS

VWI k V V V

L

' n oxn n ox

ox

k Ct

'

2(1 )

2

nD GS T DS

k WI V V V

L

Linear Region: DS GS TV V V

Saturation Mode: DS GS TV V V

Process Transconductance

Parameter

Channel Length

Modulation

Computation of VIH and VIL

15

Let g＝－1 and In=Ip

Solve for VIH and VIL

( ) ( || )out

mp mn op on

in

Vg g g r r

V

1 1

( | |) ( ) ( ) 1p DD in Tp n in Tn

Dp Dn

g k V V V k V VI I

Solution

22

/ 2 1 / 2 1 ( )Dn n in Tn out Dp p DD in Tp DD outI k V V V I k V V V V V

Switching threshold VM

VOUT=VIN => VM=f(VM)

Switching threshold VM is the function of device size

Combine VM=f(VM)

IN=IP

Solve for： VM

16

Long-channel VM

17

r

VVVrV

TnTpDD

M

1

|)|(

2

DDM

VV

pnk k ＝p

n

nW

W

p

For symmetric characteristics

p

n

kr

k

1r ＝

2 2( ) ( | |)2 2

pn

M Tn DD M Tp

kkV V V V V

18

100

101

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

MV(V

)

Wp /Wn

19

Short-channel VM

( ) ( ) 02 2

DSATpDSATnn DSATn M Tn p DSATp M DD Tp

VVk V V V k V V V V

( )2 2 with

1

DSATpDSATnTn DD Tp

p DSATp satp p

M

n DSATn satn n

VVV r V V k V v W

V rr k V v W

Solving for VM yields

Design rule

The channel width of PMOS should be times larger than

that of NMOS for the widest noise margin and symmetric

characteristics.

In reality， to save the area.

VM can be adjusted by changing to overcome noise。

=> the rise of Wp results in VM increase, closer to VDD; the rise

of Wn results in VM decrease, closer to GND 。

20

p

n

p

n

nW

W

p

nW

Wp

Design and the property

of CMOS inverter

210 0.5 1 1.5 2 2.5

0

0.5

1

1.5

2

2.5

Vin

(V)

Vo

ut(V

)

1. Good PMOS

Bad NMOS

2. Good NMOS

Bad PMOS

Nominal

1. PMOS pull-up

current is larger

than NMOS pull-

down current.

2. NMOS pull-

down current is

larger than PMOS

pull-up current.

Regeneration（Noise immunity）

22

Regeneration Non-regeneration

Inverter chain

23

Gain of CMOS inverter

24

0 0.5 1 1.5 2 2.5-18

-16

-14

-12

-10

-8

-6

-4

-2

0

Vin

(V)

gain

Feedback

Cgd is the coupling capacitance between gate and drain，

resulting in feedback。

25

0 0.5 1 1.5 2 2.5

x 10-10

-0.5

0

0.5

1

1.5

2

2.5

3

t (sec)

Vout(V

)

FAN IN and FAN OUT

26

• The more the fan out is，the lower the output is.

Solution: decrease the output impedance of driver。

• The more the fan out is, the larger the load is and the

larger the delay is.

• Fan in is the fan out of the previous inverter. The

more the fan in is, the larger self-capacitance is and

the larger the load of the previous inverter is.

Ideal inverter

g= （regeneration）

NMH=NML=VDD/2，VM=VDD/2.（noise immunity）

The input impedance is .（fan out is unlimited large）

The output impedance is zero. (fan in is zero)

27

Actual inverter

Large noise margin.

The output level is independent of inverter size.

Low output impedance

High input impedance

28

Vout

Vin0.5 1 1.5 2 2.5

0.5

11

.52

2.5

NMOS resPMOS off

NMOS satPMOS sat

NMOS offPMOS res

NMOS satPMOS res

NMOS resPMOS sat

Inverter

Delay

29

30

Two Inverters

Connect

in Metal

Share power and ground

Abut cells

VDD

31

Capacitance model of the inverter chain

32

MILLER effect

Calculation of capacitance

The load capacitance CL includes Cgd12, Cdb12,

Cg3 ,Cg4 and Cw .

33

Capacitor Expression

Cgd1 (NMOS gate-drain capacitance) 2CGDOnWn

Cgd2 (PMOS gate-drain capacitance) 2CGDOpWp

Cdb1 (NMOS diffusion capacitance) KeqnADnCJ+KeqswnPDnCJSW

Cdb2 (PMOS diffusion capacitance) KeqpADpCJ+KeqswpPDpCJSW

Cg3 (NMOS gate capacitance) (CGDOn+CGSOn)Wn+CoxWnLn

Cg4 (PMOS gate capacitance) (CGDOp+CGSOp)Wp+CoxWpLp

CW (wire capacitance) From extraction

CL (load capacitance) sum

Diffusion capacitance (Cdb)

The capacitance between drain and bulk is due to the

reversed-biased pn-junction.

Nonlinear and dependent on applied voltage.

Linear approximation is Ceq=KeqCj0

Cj0 is the junction capacitance per unit area under

zero-bias conditions.

34

1 10

0 0( )(1 )

mm m

eq high low

high low

K V VV V m

the built-in potential and m the grading coefficient of the junction0

Delay－solution

35

VDD

Vout

Vin = VDD

CLIav

tpHL = CL Vswing/2

Iav

CL

kn VDD

~

36

VDD

Vout

Vin = VDD

Ron

CL

tpHL = f(Ron.CL)

= 0.69 RonCL

t

Vout

VDD

RonCL

1

0.5

ln(0.5)

0.36

37

on eqR R

2

1 3 7(1 )

(1 ) 4 9

2

DD

DD

V

DD

eq DD

DD V DSAT DSAT

VVR dV V

V I V I

2

'

2

DSATDSAT DD T DSAT

VWI k V V V

L

ln(2) 0.69pHL eqn L eqn Lt R C R C

0.69pLH eqp Lt R C

0.69 ( )2 2

pHL pLH eqp eqn

p L

t t R Rt C

Inverter delay

38

2

1)(

V

V

Lpvi

dvCt

L

pLH

p DD

Ct

k V L

pHL

n DD

Ct

k V

1 1( )

2 2*

pLH pHL L

p

DD n p

t t Ct

V k k

Optimization of NMOS/PMOS ratio

Optimize Wp/Wn for the best speed performance

39

p

n

p

n

k

k

n

p

W

W

Wgndn

WgngpdndpL

CCC

CCCCCC

))(1(

)()(

(1 )( )1 1( ) (1 )

2* 2

dn gn W nL

p

DD n p DD n p

C C CCt

V k k V k

opt

0

(1 )

p

n W

p dn gn

t

C

C C

Let

then

NMOS/PMOS ratio

40

1 1.5 2 2.5 3 3.5 4 4.5 53

3.5

4

4.5

5x 10

-11

t p(s

ec)

tpLH tpHL

tp a = Wp/Wn

41

0 0.5 1 1.5 2 2.5

x 10-10

-0.5

0

0.5

1

1.5

2

2.5

3

t (sec)

Vout(V

)

Transient response（short-channel）

tp = 0.69 CL (Reqn+Reqp)/2

tpLH tpHL

2

2

'

1 3 7(1 )

(1 ) 4 9

2

with 2

DD

DD

V

DD

eq DD

DD V DSAT DSAT

DSAT

DSAT DD T DSAT

VVR dV V

V I V I

VWI k V V V

L

Delay is the function of VDD

42

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VDD

(V)

t p(n

orm

aliz

ed)

'0.69 0.52

( / ) / 2

L DD L DDpHL

DSATn n n DSATn DD Tn DSATn

C V C Vt

I W L k V V V V

Delay is the function of device size

43

2 4 6 8 10 12 142

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8x 10

-11

S

t p(s

ec)

Self-capacitance

increases with

device size and

begins to play a

dominant role.

Notes：fixed load

Delay is the function of the rise time

44

t pH

L(n

sec)

0.35

0.3

0.25

0.2

0.15

trise (nsec)

10.80.60.40.20

2 2

( ) ( / 2)pHL pHL step rt t t

Delay is the function of fanout

Delay linearly increases with fanout.

（Notes：fanout capacitance dominants the load capacitance

by ignoring the self capacitance and interconnect capacitance）

45

( ) (0) ( (1) (0))

( ) :

(0) : 0 ;

(1) :1 ;

p p p p

p

p

p

t N t N t t

t N N

t

t

fanout；

fanout

fanout

High-speed IC design

Reduce load capacitance

（including self capacitance, wire capacitance and fan out

capacitance）

Raise kn and kp

Note: increase W/L =>the rise of W increases the area and self

capacitance.

Increase VDD

Cost: the rise of power

46

Homework

47

CMOS Inverter

48

Polysilicon

InOut

Metal1

VDD

GND

PMOS

NMOS

49

50

NMOS:

the bottom plate diffusion capacitance

the sidewall diffusion capacitance

00.5, 0.9m

PMOS:

the bottom plate diffusion capacitance

the sidewall diffusion capacitance

00.44, 0.9m

00.48, 0.9m

00.32, 0.9m

51

1. Calculate the load capacitance of the first inverter.

2. Calculate the on resistance of CMOS inverter.

3. Calculate the propagation delay.

4. （optional）Simulate CMOS inverter with the following

transistor models and compare the delay with the

calculation results.

.MODEL N NMOS

+ LEVEL = 3

+ VTO = 0.41

+ TOX = 5.75E-09

+ NSUB =2.0E+18

+ UO = 350

+ CJSO =0.31e-9

+ CJ = 2e-3

+ CJSW = 2.8e-9

.MODEL P PMOS

+ LEVEL = 3

+ VTO = -0.41

+ TOX = 5.75E-09

+ NSUB = 2.0E+18

+ UO = 175

+ CJSO =0.27e-9

+ CJ = 1.91e-3

+ CJSW = 2.2e-10