Memory Management

CSC501 Operating Systems Principles

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Previous Lecture

q Memory ManagementQ Logical address / physical addressQ Segmentation

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CPU

MMU

Memory I/O Devices

Logical Addresses

Physical Addresses

Segmentation and Paging

q SegmentationQ Each process divided into variable-sized segmentsQ All process segments loaded into dynamic

partitionsq PagingQ Memory divided into equal-sized framesQ All process pages loaded into frames that are not

necessarily contiguous

Pagingq Processes see a contiguous virtual address spaceQ The virtual address space into equal sized pieces

called pages

q The memory unit sees a contiguous physical address spaceQ The physical address space into equal sized

pieces called frames

q sizeof(page) = sizeof(frame)Q size usually a power of 2 between 512 and 8192

bytes

Pagingq Page tableQ Stores mappings from virtual to physical addressQ Entries contain:v Physical frame numberv State: valid/invalid, access permission, reference,

modified, and caching bitsq Paging is transparent to the programmer

Question: Do we still have external

fragmentation problem? How about internal fragmentation problem?

q Address generated by CPU is divided into:Q Page number (index) (p) –

used as an index into a pagetable which contains base address of each page in physical memory

Q Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit

offsetindexvirtual address

offsetframephysical address

page table

Address Translation Scheme

Address Translation Architecture

Implementation of Page Table

q Page table is kept in main memoryq Page-table base register (PTBR) points to the

page tableq Page-table length register (PRLR) indicates

size of the page tableq In this scheme every data/instruction access

requires two memory accesses. One for the page table and one for the data/instruction.

Translation Look-aside Buffers (TLBs)

q Translation on every memory access -> must be fast

q What to do? Q Cache for page table entries is called the

Translation Lookaside Buffer (TLB)v Typically fully associativev Typically around 256 entries

q On every memory access, we look for the page àframe mapping in the TLB

Associative Memory

qAssociative memory – parallel search

Address translation (A´, A´´)QIf A´ is in associative register, get frame # outQOtherwise get frame # from page table in

memory

Page # Frame #

TLB Miss

q What if the TLB does not contain the right page table entry (or TLB miss)?Q Find a free entry (if not, evict an existing entry)v Replacement policy?

Q Bring in the missing entry from the PTq TLB misses can be handled in hardware or

softwareQ Software allows application to assist in

replacement decisions

Paging Hardware With TLB

Memory Protection

q Memory protection implemented by associating protection bit with each frame

q Valid-invalid bit attached to each entry in the page table:Q “valid” indicates that the associated page is in

the process’ logical address space, and is thus a legal page

Q “invalid” indicates that the page is not in the process’ logical address space

q Read/Write/Execute permissions also associated with each page table entry

Memory Protection

01101000100000100

01101000100110110

000100 110110000011 X000010 100101000001 X000000 X

000101 X000110 X000111 X001000 001011

Page Table

Page Frame

Physical Memory

Page Number Page Offset

RRWRWR

RW

RRWRWRW

Protection

Page Table Structure

q Hierarchical Page Tables

q Hashed Page Tables

q Inverted Page Tables

Hierarchical Page Tables

q Break up the logical address space into multiple page tables

q A simple technique is a two-level page tableQ A logical address (on 32-bit machine with 4K

page size) is divided into:va page number consisting of 20 bitsva page offset consisting of 12 bitsQ Since the page table is paged, the page number is

further divided into:va 10-bit page number va 10-bit page offset

qThus, a logical address is as follows:

where pi is an index into the outer page table, and p2is the displacement within the page of the outer page table

page number page offset

pi p2 d

10 10 12

Two-Level Paging Example

Two-Level Paging Example

q Address-translation scheme for a two-level 32-bit paging architecture

Hashed Page Tables

q The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location.

q Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted.

q Common in address spaces > 32 bits

Hashed Page Tables

Inverted Page Tables

q One entry for each real page of memoryq Entry consists of the virtual address of the

page stored in that real memory location, with information about the process that owns that page

q Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs

q Use hash table to limit the search to one — or at most a few — page-table entries

Inverted Page Tables

Memory Hierarchy

Registers

Cache

Memory

Question: What if we want to support programs that require more memory than what’s available in the system?

Registers

Cache

Memory

Virtual Memory

Memory Hierarchy

Answer: Pretend we had something bigger=> Virtual Memory

Background

q Virtual memory – separation of user logical memory from physical memory.Q Only part of the program needs to be in memory

for executionQ Logical address space can therefore be much

larger than physical address space. v Gives the programmer the illusion of a virtual

address space that may be larger than the physical address space

Background

q Motivated byQ Convenience: the programmer does not have to

deal with the fact that individual machines may have very different amounts of physical memory

Q Higher degree of multiprogramming: processes are not loaded as a whole. Rather they are loaded on demand.

q Virtual memory can be implemented via:Q Demand segmentationQ Demand paging (most common)

Demand Paging

q Bring a page into memory only when it is neededQ Less I/O neededQ Less memory needed Q Faster responseQ More users

q Page is needed ⇒ reference to itQ invalid reference ⇒ abortQ not-in-memory ⇒ bring to memory

Page Faultq If there is ever a reference to a page, first

reference will trap to OS ⇒ page fault

q Page fault handler looks at the cause and decide:Q Invalid reference ⇒ abortQ Just not in memoryv Get empty framev Swap page into framev Reset tables, valid bit = 1v Restart instruction

Steps in Handling a Page Fault

A

C

E

0

1

2

3

4

B

D

Logical Memory 9 V

i2 V

i5 V

01234

Page Table

TLB miss

Restart Process

Update PTE

Find Frame

A C

E

B

D

Get page from backing store

Bring in page

Page faulthandler

Page fault

C

E

A

10

123

6789

54

0

Physical Memory

1 off

TLB

2

1

34

5

67

8

CR3

Question: Where is the page table?

Focus I: Page table

Focus II: Page replacement

Next Lecture

q Lab3q Page Replacement Algorithms

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