Lab vlsi

CONTENTS

1)Study of Simulation using tools.

2)Design Entry and Simulation of Combinational Logic Circuits

a)Basic logic gates

b)Half adder and full adder

c)Half Subtractor and full Subtractor

d)8 bit adder

e)4 bit multiplier

f)Encoder and Decoder

g)Address Decoder

h)Multiplexer

3)Design Entry and Simulation of Sequential Logic Circuits

a)Flip-Flops

b)Counter

c)PRBS generator

d)Accumulator

4)Study of Synthesis tools

5)Place and Route and Back annotation for FPGAs

6)Schematic Entry and SPICE Simulation

a)CMOS Inverter

b)Universal Gate

c)Differential Amplifier

7)Layout of a CMOS Inverter

8)Design of a 10 bit number controlled oscillator

9)Automatic Layout Generation

VLSI DESIGN

VLSI LAB MANUAL

ASIC DESIGN FLOW

ASIC FLOW

Fig 1: Waveform Editor - Initialize Timing Dialog Box

Expt. No : STUDY OF SIMULATION TOOLS

Date :

To study the Simulation tools

THEORY:

Creating a Test Bench for Simulation:

In this section, you will create a test bench waveform containinginput stimulus you can use to simulate the counter module. This test bench waveform is a graphical view of a test bench. It is used with asimulator to verify that the counter design meets both behavioral andtiming design requirements. You will use the Waveform Editor to create atest bench waveform (TBW) file.

1.Select the counter HDL file in the Sources in Project window.

2.Create a new source by selecting Project -New Source.

3.In the New Source window, select Test Bench Waveform asthe source type, and type test bench

in the File Name field.

4.Click Next.

5.The Source File dialog box shows that you are associating thetest bench

with the source file: counter.v Click Next.

6.Click Finish. You need to set initial values for your test benchwaveform in the Initialize Timing dialog box before the test bench waveform editing window opens.

7.Fill in the fields in the Initialize Timing dialog box usingthe information below:

Clock Time High:20 ns. Clock Time Low:20 ns. Input Setup Time:10 ns. Output Valid Delay:10 ns.

Initial Offset:0 ns

Global Signals:GSR (FPGA)

Leave the remaining fields with their default values.

8.Click OK to open the waveform editor. The blue shaded areas areassociated with each input signal and correspond to the Input Setup Timein the Initialize Timing dialog box. In this tutorial, the input transitionsoccur at the edge of the blue cells located under each rising edge of theCLOCK input.

Fig 2: Waveform Editor - Test Bench

9.In this design, the only stimulus that you will provide is on theDIRECTION port. Make the transitions as shown below for theDIRECTION port:

Click on the blue cell at approximately the 300 ns clock transition. Thesignal switches to high at this point.

Click on the blue cell at approximately the 1400 ns clocktransition. The signal switches to high again.

10.Select File -Save to save the waveform. In the Sources in Projectwindow, the TBW file is automatically added to your project.

11.Close the Waveform Editor window

VLSI LAB MANUAL

Simulating the Behavioral Model (ISE Simulator):

If you are using ISE Base or Foundation, you can simulate your design with theISE Simulator. If you wish to simulate your design with a ModelSim simulator,skip this section and proceed to the “Simulating the Behavioral Model(ModelSim)” section.

Fig 3: Simulator Processes for Test Bench

Fig 4: Behavioral Simulation in ISE Simulator

To run the integrated simulation processes in ISE:

1.Select the test bench waveform in the Sources in Project window. You cansee the Xilinx ISE Simulator processes in the Processes for Source window.

2.Double-click the Simulate Behavioral Model process. The ISE Simulatoropens and runs the simulation to the end of the test bench.

3.To see your simulation results, select the test bench tab and zoom in on thetransitions. You can use the zoom icons in the waveform view, or right clickand select a zoom command. The ISE window, including the waveform view.

4.Zoom in on the area between 300 ns and 900 ns to verify that thecounter is counting up and down as directed by the stimulus on theDIRECTION port.

5.Close the waveform view window. You have completed simulation of yourdesign using the ISE Simulator.

Simulating the Behavioral Model (ModelSim):

If you have a ModelSim simulator installed, you can simulate your design usingthe integrated ModelSim flow. You can run processes from within ISE whichlaunches the installed ModelSim simulator.

To run the integrated simulation processes in ISE:

1.Select the test bench in the Sources in Project window. You can seeModelSim Simulator processes in the Processes for Source window in Fig4

Fig 5: Simulator Processes for Test Bench

Fig 6: Behavioral Simulation in ModelSim

2.Double-click the Simulate Behavioral Model process. The ModelSimsimulator opens and runs your simulation to the end of the test bench. TheModelSim window, including the waveform, should look likeFig 6.To see your simulation results, view the Wave window.

1. Right-click in the Wave window and select a zoom command.

2.Zoom in on the area between 300 ns and 900 ns to verify that thecounter is counting up and down as directed by the stimulus on theDIRECTION port.

3.Close the ModelSim window

RESULT:

DESIGN ENTRY AND SIMULATION OF COMBINATIONAL LOGIC CIRCUITS

BASIC LOGIC GATES

Expt. No :

To implement basic logic gates using Verilog HDL.

APPARATUS REQUIRED:

PC with Windows XP. XILINX, ModelSim software. FPGA kit. RS 232 cable.

PROCEDURE:

Write and draw the Digital logic system. Write the Verilog code for above system. Enter the Verilog code in Xilinx software. Check the syntax and simulate the above Verilog code (usingModelSim or Xilinx) and verify

the output waveform as obtained. Implement the above code in Spartan III using FPGA kit.

PROGRAM:

AND Gate: // Module Name: Andgate

module Andgate (i1, i2,out);

input i1, i2;

output out;

and (out,i1,i2);

endmodule

// Module Name: Stimulus.v module

module stimulus;

//Inputs

reg i1, i2;

//Outputs

wire out;

// Instantiate the Unit Under Test (UUT)

Andgate uut1 (.i1(i1),.i2(i2),.out(out));

initial

$display("\t\t\t\tAND Gate");

$display("\t\t--------------------------------------");

$display("\t\tInput1\t\t Input2\t\t Output");

$display("\t\t--------------------------------------");

$monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out);

#4 $display("\t\t--------------------------------------");

initial begin

i1=1'b0;

i2=1'b0;

#1 i2=1'b1;

#1 i1=1'b1;

i2=1'b0;

#1 i1=1'b1;

i2=1'b1;

#1$stop;

endendmodule

Symbol

TRUTH TABLE:

Simulated Waveform

PROGRAM

OR Gate:

// Module Name: Orgate

module Orgate (i1, i2,out);

input i1, i2;

output out;

or (out,i1,i2);

endmodule

module stimulus;

//Inputs

reg i1, i2;

//Outputs

wire out;

Orgate uut1 (.i1(i1),.i2(i2),.out(out));

initial

$display("\t\t\t\tORGate");

$display("\t\t--------------------------------------");

#4 $display("\t\t--------------------------------------");

initial

i1=1'b0;

i2=1'b0;

#1 i2=1'b1;

#1 i1=1'b1;

i2=1'b0;

#1 i1=1'b1;

i2=1'b1;

#1$stop;

endmodule

SYMBOL:

TRUTH TABLE:

SIMULATED WAVEFORM:

PROGRAMNOR Gate: // Module Name: Norgate

Module Norgate (i1, i2,out);

input i1, i2;

output out;

nor (out,i1,i2);

endmodule

module stimulus;

//Inputs

reg i1, i2;

//Outputs

wire out;

Norgate uut1 (.i1(i1),.i2(i2),.out(out));

initial

$display("\t\t\t\tNORGate");

$display("\t\t--------------------------------------");

#4 $display("\t\t--------------------------------------");

initial

i1=1'b0; i2=1'b0; #1 i2=1'b1;

#1 i1=1'b1; i2=1'b0; #1 i1=1'b1; i2=1'b1;

#1$stop;

endmodule

SYMBOL:

TRUTH TABLE:

Simulated Waveform

PROGRAM

XOR Gate: // Module Name:Xorgate

module Xorgate (i1, i2,out);

input i1, i2;

output out;

xor (out,i1,i2);

endmodule

//Module Name: Stimulus.v module

module stimulus;

//Inputs

reg i1, i2;

//Outputs

wire out;

Xorgate uut1 (.i1(i1),.i2(i2),.out(out));

initial

$display("\t\t\t\tXORGate");

$display("\t\t--------------------------------------");

#4 $display("\t\t--------------------------------------");

initial

i1=1'b0; i2=1'b0; #1 i2=1'b1;

#1 i1=1'b1; i2=1'b0; #1 i1=1'b1; i2=1'b1;

#1$stop;

endmodule

SYMBOL:

TRUTH TABLE:

SIMULATED WAVEFORM:

PROGRAMXNOR Gate: // Module Name: Xnorgatemodule Xnorgate (i1, i2,out);

input i1, i2;

output out;xnor (out,i1,i2);

endmodule

module stimulus;

//Inputs

reg i1, i2;

//Outputs

wire out;

Xnorgate uut1 (.i1(i1),.i2(i2),.out(out));

initial begin$display("\t\t\t\tXNORGate");

$display("\t\t--------------------------------------");

#4 $display("\t\t--------------------------------------");

initial

begini1=1'b0; i2=1'b0; #1 i2=1'b1;

#1 i1=1'b1; i2=1'b0; #1 i1=1'b1; i2=1'b1;

#1$stop;

endmodule

SYMBOL:

TRUTH TABLE:

SIMULATED WAVEFORM:

PROGRAMNOT Gate: // Module Name: Notgatemodule Notgate (i1, out);

input i1;

output out;

not (out,i1);

endmodule

module stimulus;

//Inputs

reg i1;

//Outputs

wire out;

Notgate uut1 (.i1(i1),. out(out));

initial

$display("\t\t\t\tNOTGate");

$display("\t\t--------------------------------------");

$display("\t\tInput1\t\t Output");

$display("\t\t--------------------------------------");

$monitor("\t\t\t%b \t\t%b ",i1 ,out);

#4 $display("\t\t--------------------------------------");

initial begini1=1'b0;#1 i1=1'b1; #1 $stop;endendmodule

SYMBOL:

TRUTH TABLE:

SIMULATED WAVEFORM:

PROGRAM

Buffer:

// Module Name: Buffer

module Buffer (i1, out);

input i1;

output out;

buf (out,i1);

endmodule

module stimulus;

//Inputs

reg i1;

//Outputs

wire out;// Instantiate the Unit Under Test (UUT)

Buffer uut1 (.i1(i1),. out(out));

initial

$display("\t\t\t\tBuffer");$display("\t\t--------------------------------------");

$display("\t\tInput1\t\t Output");$display("\t\t--------------------------------------");

$monitor("\t\t\t%b \t\t%b ",i1 ,out);

#4 $display("\t\t--------------------------------------");

initial

begini1=1'b0;#1 i1=1'b1;

#1 $stop;

endmodule

SYMBOL:

TRUTH TABLE:

SIMULATED WAVEFORM:

RESULT:

Expt. No: HALF ADDER AND FULL ADDER

Date :

To implement half adder and full adder using Verilog HDL.

APPARATUS REQUIRED:

PC with Windows XP XILINX, ModelSim software. FPGA kit RS 232 cable.

PROCEDURE:

Write and draw the Digital logic system. Write the Verilog code for above system. Enter the Verilog code in Xilinx software. Check the syntax and simulate the above Verilog code (using ModelSimor Xilinx) and verify

the output waveform as obtained. Implement the above code in Spartan III using FPGA kit

PROGRAM:

Half Adder:

// Module Name: HalfAddr

module HalfAddr(sum, c_out, i1, i2);

output sum, c_out;

input i1;

input i2;

xor(sum,i1,i2);

and(c_out,i1,i2);

endmodule

//Module Name: Stimulus.v

module Stimulus_v;

// Inputs

reg i1,i2;

// Outputs

wire sum, c_out;

HalfAddr uut (.sum(sum),.c_out(c_out),.i1(i1),.i2(i2));

initial

$display("\t\t\Half Adder");

$display("\t\tInput1\t\t Input2\t\t Carry\t\t Sum");

$display("\t\t----------------------------------------");

$monitor(“\%b\t\t%b\t\t%b\t\t”,i1,i2,c_out,sum);

$display("\t\t ---------------------------------------“);

initial

i1=1'b0; i2=1'b0; #1 i2=1'b1;#1 i1=1'b1; i2=1'b0;

#1 i1=1'b1; i2=1'b1;

#1 $stop;

endmodule

SYMBOL:

TRUTH TABLE:

SIMULATED WAVEFORM:

PROGRAM

Full Adder:

// Module Name: FullAddr

module FullAddr(i1, i2, c_in, c_out, sum);

input i1, i2, c_in;

output c_out, sum;

wire s1,c1,c2;

xor n1(s1,i1,i2);

and n2(c1,i1,i2);

xor n3(sum,s1,c_in);

and n4(c2,s1,c_in);

or n5(c_out,c1,c2);

endmodule

// Module Name: Stimulus.v

module Stimulus_v;

// Inputsreg i1 , i2 , c_in;

// Outputswire c_out, sum;

FullAddr uut (.i1(i1),.i2(i2),.c_in(c_in),.c_out(c_out),.sum(sum));

initial

$display("\t\t\t\t\t\tFull Adder");

$display("\t\t----------------------------------------------------------------");

$display("\t\ti1\t\ti2\t\tC_in\t\t\tC_out\t\tSum");

$display("\t\t----------------------------------------------------------------");

$monitor(" t\t%b\t\t%b\t\t%b\t\t\t%b\t\t%b",i1,i2,c_in,c_out,sum);

#9 $display("\t\t-------------------------------------------------------------------");

initial

#1i1 = 0;i2 = 0;c_in = 0;

#1 i1 = 0;i2 = 0;c_in = 0;

#1 i1 = 0;i2 = 0;c_in = 1;

#1 i1 = 0;i2 = 1;c_in = 0;

#1 i1 = 0;i2 = 1;c_in = 1;

#1 i1 = 1;i2 = 0;c_in = 0;

#1 i1 = 1;i2 = 0;c_in = 1;

#1 i1 = 1;i2 = 1;c_in = 0;

#1 i1 = 1;i2 = 1;c_in = 1;

#2 $stop;

endmodule

LOGIC DIAGRAM:

TRUTH TABLE:

SIMULATED WAVEFORM:

RESULT:

Expt. No: HALF SUBTRACTOR & FULL SUBTRACTOR

Date :

To implement half subtractor and full subtractor using Verilog HDL.

APPARATUS REQUIRED:

PC with Windows XP XILINX, ModelSim software. FPGA kit RS 232 cable.

PROCEDURE:

Write and draw the Digital logic system. Write the Verilog code for above system. Enter the Verilog code in Xilinx software. Check the syntax and simulate the above verilog code (using ModelSim orXilinx) and verify the

output waveform as obtained. Implement the above code in Spartan III using FPGA kit.

PROGRAM:

Half Subtractor: // Module Name: HalfSub

module HalfSub(i0, i1, bor, dif);

input i0, i1;

output bor,dif;

wire i0n;not(i0n,i0);xor(dif,i0,i1);

and(bor,i0n,i1);

endmodule

// ModuleName:Stimulus.v

module Stimulus_v;

// Inputs

reg i0, i1;

//Outputs

wire bor; wire dif;

//Instantiate the Unit Under Test (UUT)

HalfSub uut (.i0(i0),.i1(i1),.bor(bor),.dif(dif));

initial

$display("\t\t\t\t\tHalf Subtractor");

$display("\t\t----------------------------------------------------------");

$display("\t\tInput1\t\t Input2\t\t Borrow\t\t Difference");

$display("\t\t----------------------------------------------------------");

$monitor("\t\t\t%b\t\t%b\t\t%b\t\t%b",i0,i1,bor,dif);

#4 $display("\t\t-----------------------------------------------------------");

initial

i0=1'b0;

i1=1'b0;

#1 i1=1'b1;

#1 i0=1'b1;

i1=1'b0;

#1 i0=1'b1;

i1=1'b1;

#1$stop;

endmodule

LOGIC DIAGRAM:

TRUTH TABLE:

SIMULATED WAVEFORM

PROGRAM

Full Subtractor:

// Module Name: FullSub

module FullSub(b_in, i1, i0, b_out, dif);

input b_in;

input i1, i0;

output b_out,dif;

assign {b_out,dif}=i0-i1-b_in;

endmodule

module Stimulus_v;

// Inputsreg b_in, i1,i0;/

/ Outputs

wire b_out;

wire dif;

FullSub uut (.b_in(b_in),.i1(i1),.i0(i0),.b_out(b_out),.dif(dif));

initial

$display("\t\t\t\t\t\tFull Subtractor");

$display("\t\t-------------------------------------------------------------------------");

$display("\t\tB_in\t\tI1\t\ti0\t\t\tB_out\t\tDifference");

$display("\t\t-------------------------------------------------------------------------");

$monitor("\t\t%b\t\t%b\t\t%b\t\t\t %b\t\t\t %b",b_in,i1,i0,b_out,dif);

#9 $display("\t\t-------------------------------------------------------------------------");

initial

// Initialize Inputs

b_in = 0;i1 = 0;i0 = 0;

#1 b_in = 0;i1 = 0;i0 = 0;

#1 b_in = 0;i1 = 0;i0 = 1;

#1 b_in = 0;i1 = 1;i0 = 0;

#1 b_in = 0;i1 = 1;i0 = 1;

#1 b_in = 1;i1 = 0;i0 = 0;

#1 b_in = 1;i1 = 0;i0 = 1;

#1 b_in = 1;i1 = 1;i0 = 0;

#1 b_in = 1;i1 = 1;i0 = 1;

#2 $stop;

endmodule

LOGIC DIAGRAM:

TRUTH TABLE:

SIMULATED WAVEFORM:

RESULT:

Expt. No: 4BIT MULTIPLIER

Date :

To implement four bit multiplier using Verilog.

APPARATUS REQUIRED:

PC with Windows XP XILINX, ModelSim software FPGA kit RS 232 cable.

PROCEDURE:

Write and draw the Digital logic system. Write the Verilog code for above system. Enter the Verilog code in Xilinx software. Check the syntax and simulate the above verilog code (usingModelSim or Xilinx) and verify the

PROGRAM

MULTIPLIER

module multi(a,b, c);

input [3:0] a,b;

output [7:0] c;

assign c = a * b;

endmodule

STIMULUS

module testbenchmulti ;

//inputsreg [3:0] a,b;

//outputswire [7:0] c;

multi multipl(.c(c),.a(a),.b(b));

initial begina=4'b0; b=4'b0;

//wait 100ns for global reset to finish

#100; a=4'd3; b=4'd4;

#100; a=4'd3; b=4'd5;

#100; a=4'd2; b=4'd4;

endmodule

BLOCK DIAGRAM:

SIMULATED WAVEFORM:

RESULT:

Expt. No: 8 BIT ADDER

Date :

To implement the 8-bit adder using Verilog.

APPARATUS REQUIRED:

PC with Windows XP XILINX, ModelSim software FPGA kit RS 232 cable.

PROCEDURE:

Write and draw the Digital logic system. Write the Verilog code for above system. Enter the Verilog code in Xilinx software. Check the syntax and simulate the above verilog code (using ModelSimor Xilinx) and verify the Implement the above code in Spartan III using FPGA kit.

PROGRAM

8 BIT ADDER

module adder(a,b, s,c);

input [7:0] a,b;

output [7:0] s,c;

assign {c,s} = a + b;

endmodule

STIMULUS:

module testbenadder;

//Inputs

reg [7:0] a,b;

//outputs

wire [7:0] s;

wire c;

adder add(.s(s),.c(c),.a(a),.b(b));

initial

//initialize input

a=8'd0; b=8'd0;

//wait 100ns for global reset to finish

#100; a=8'd1; b=8'd0;

#100; a=8'd9; b=8'd5;

#100; a=8'd5; b=8'd7;

endmodule

BLOCK DIAGRAM:

RESULT:

Expt No: IMPLEMENTATION OF 4x2 ENCODER AND

Date: 2x4 DECODER

To implement 4x2 Encoder and 2 x 4 Decoder Verilog HDL.

APPARATUS REQUIRED:

PROCEDURE:

PROGRAM:

Encoder: // Module Name: Encd2to4

module Encd2to4(i0, i1, i2, i3, out0, out1);

input i0,i1, i2, i3;

output out0, out1;

reg out0,out1;

always@(i0,i1,i2,i3)

case({i0,i1,i2,i3})

4'b1000:{out0,out1}=2'b00;

4'b0100:{out0,out1}=2'b01;

4'b0010:{out0,out1}=2'b10;

4'b0001:{out0,out1}=2'b11;

default:

$display("Invalid");

endcase

endmodule

module Stimulus_v;//

Inputsreg i0, i1, i2, i3;//

Outputswire out0, out1;

Encd2to4 uut(.i0(i0),.i1(i1),.i2(i2),.i3(i3),.out0(out0),.out1(out1));

initial

$display("\t\t 4to2 Encoder");$display("\t\t------------------------------");

$display("\t\tInput\t\t\tOutput");

$display("\t\t------------------------------");

$monitor("\t\t%B%B%B%B\t\t\t %B%B",i0,i1,i2,i3,out0,out1);

#4 $display("\t\t-------------------------------");

initial

i0=1; i1=0; i2=0; i3=0;

#1 i0=0; i1=1; i2=0; i3=0;

#1 i0=0; i1=0; i2=1; i3=0;

#1 i0=0; i1=0; i2=0; i3=1;

#1 $stop;

endmodule

BLOCK DIAGRAM:

TRUTH TABLE:

SIMULATED WAVEFORM:

PROGRAMDecoder:

// Module Name: Decd2to4

module Decd2to4(i0, i1, out0, out1, out2, out3);

input i0, i1;

output out0, out1, out2, out3;

regout0,out1,out2,out3;

always@(i0,i1)

case({i0,i1})

2'b00:{out0,out1,out2,out3}=4'b1000;

2'b01:{out0,out1,out2,out3}=4'b0100;

2'b10:{out0,out1,out2,out3}=4'b0010;

2'b11:{out0,out1,out2,out3}=4'b0001;

default:$display("Invalid");

endcase

endmodule

/ Module Name: Stimulus.v

module Stimulus_v;

// Inputs

reg i0, i1;

//Outputs

wire out0, out1, out2, out3;

Decd2to4 uut (.i0(i0),.i1(i1),.out0(out0),.out1(out1),.out2(out2),.out3(out3));

initial

$display(“\t\t 2to4 Decoder”);

$display(“\t\t --------------------------”);

$display(“\t\t Input \t\t Output”);

$display(“\t\t --------------------------”);

$monitor(“\t\t %b%b\t\t\t %b%b%b %b”,i0,i1,out0,out1,out2,out3);

#4 $display(“\t\t --------------------------”);

initial

i0=0;i1=0;

#1 i0=0;i1=1;

#1 i0=1;i1=0;

#1 i0=1;i1=1;

#1 $stop;

endmodule

TRUTH TABLE:

SIMULATED WAVEFORM:

RESULT:

Expt. No: MULTIPLEXER & DEMULTIPLEXER

Date :

To implement Multiplexer & Demultiplexer using Verilog HDL.

APPARATUS REQUIRED:

PROCEDURE:

PROGRAM:

Multiplexer: // Module Name: Mux4to1

module Mux4to1(i0, i1, i2, i3, s0, s1, out);

input i0, i1, i2, i3, s0, s1;

output out;

wire s1n,s0n;

wire y0,y1,y2,y3;

not (s1n,s1);

not (s0n,s0);and (y0,i0,s1n,s0n);

and (y1,i1,s1n,s0);

and (y2,i2,s1,s0n);

and (y3,i3,s1,s0);

or (out,y0,y1,y2,y3);

endmodule

/ Module Name: Stimulus.v

module Stimulus_v;

// Inputs

reg i0, i1, i2,,i3, s0, s1;

//Outputs

wire out;

Instantiate the Unit Under Test (UUT)

Mux4to1 uut (.i0(i0),.i1(i1),.i2(i2),.i3(i3),.s0(s0),.s1(s1),.out(out));

initial

$display(“\t\t\t4to1 Multiplexer”);

$display(“\t\t-------------------------“);

#1 $display(“\t\t\t Input=%b%b%b%b”,i0,i1,i2,i3);

$display(“\t\t----------------------------------“);

$display(“\t\tSelector \t\t\t\t Output”);

$display(“\t\t----------------------------------“);

$monitor(“\t\t{%b,%b}\t\t\t\t%b”,s0,s1,out);

#4 $display(“\t\t-----------------------------------------------“);

initial

i0=1; i1=0; i2=1; i3=1;

#1 s0=0; s1=0;

#1 s0=1; s1=0;

#1 s0=0; s1=1;

#1 s0=1; s1=1;

#1 $stop;

endmodule

LOGIC DIAGRAM:

TRUTH TABLE:

SIMULATED WAVEFORM:

PROGRAM

Demultiplexer:

// Module Name: Dux1to4

module Dux1to4(in, s0, s1, out0, out1, out2, out3);

input in, s0, s1;output out0, out1, out2,out3;

wire s0n,s1n;

not(s0n,s0);

not(s1n,s1);

and (out0,in,s1n,s0n);

and (out1,in,s1n,s0);

and (out2,in,s1,s0n);

and (out3,in,s1,s0);

endmodule

module Stimulus_v;//Inputsreg in, s0, s1;//

Outputswire out0, out1, out2, out3;//

Instantiate the Unit Under Test (UUT)

Dux1to4 uut (.in(in),.s0(s0),.s1(s1),.out0(out0),.out1(out1),.out2(out2),.out3(out3));

initial

$display("\t\t 1to4 Demultiplexer");

$display("\t\t------------------------------------");

#1 $display("\t\t\t\tInput=%b",in);

$display("\t\t------------------------------------");

$display("\t\tStatus\t\t\t\tOutput");

$display("\t\t------------------------------------");

$monitor("\t\t{%b,%b}\t\t\t\t%b%b%b%b",s1,s0,out0,out1,out2,out3);

#4 $display("\t\t------------------------------------");

initial

in=1;#1 s1=0;s0=0;

#1 s1=0;s0=1;

#1 s1=1;s0=0;

#1 s1=1;s0=1;

#1 $stop;

endmodule

TRUTH TABLE:

DEMULTIPLEXER

LOGIC DIAGRAM:

SIMULATED WAVEFORM:

RESULT:

Expt. No: IMPLEMENTATION OF COUNTERS

To implement Counters using Verilog HDL

APPARATUS REQUIRED:

PROCEDURE:

Write and draw the Digital logic system. Write the Verilog code for above system. Enter the Verilog code in Xilinx software. Check the syntax and simulate the above Verilog code (usingModelSim or Xilinx) and verify

the output waveform as obtained. Implement the above code in Spartan III using FPGA kit.

PROGRAM:

2- Bit Counter:

// Module Name: Count2Bit

module Count2Bit(Clock, Clear, out);

input Clock, Clear;

output [1:0] out;

reg [1:0]out;

always@(posedge Clock, negedge Clear)

if((~Clear) || (out>=4))

out=2'b00;

elseout=out+1;

endmodule

module Stimulus_v;

//Inputs

reg Clock, Clear;

//Outputs

wire [1:0] out;

Count2Bit uut (.Clock(Clock),.Clear(Clear),.out(out));

initial

$display("\t\t\t 2 Bit Counter");

$display("\t\t----------------------------------------");

$display("\t\tClock\t\tClear\t\tOutput[2]");

$display("\t\t----------------------------------------");

$monitor("\t\t %b\t\t %b \t\t %b ",Clock,Clear,out);

#28 $display("\t\t----------------------------------------");

always#1 Clock=~Clock;

initial

Clock=0;

Clear=0;

#10 Clear=1;

#18 Clear=0;

#2 $stop;

endmodule

LOGIC DIAGRAM:

SIMULATED WAVEFORM:

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