Post on 28-Nov-2015
description
Dynamic Analogue IC Design
Lab 3: Switched Capacitor Simulation
Student Name: Mark Lennon
Lecturer Name: Mark Norton
Date: 11/12/08
Essential Formulae:
Tau = Rs * Cl
Rs = 1 / (Cs * fs)
fp = 1 / ( 2 * pi * Rs * Cl)
Therefore: fp = (Cs * fs) / (2 * pi * Cl)
Rearranged: fs = (2 * pi * Cl * fp) / Cs
xdB = 20log(Gain)
Where:
Tau = The time constant
Rs = Equivalent Switched capacitor resistance
Cs = Switched capacitor capacitance
fs = Switched capacitance clock frequency
fp = pole frequency
Cl = Load capacitance
Non-Overlapping Clock
Objective: In this circuit a non-overlapping clock is required. This was achieved by using a
strategy used for a D-Type flip flop with a delay involved.
This will create an output as follows:
We can see that this clock does not have a high value for both outputs (phi1 and phi2)
Using a 1MHz clock frequency it is much harder to see that the clocks dont overlap.
The delay could be increased by including more inverters in the circuit as shown below:
NETLIST:
*************** Subcircuits *****************
.subckt Inv A Out Gnd Vdd
* S-Edit Info
* Designed by: Author Date
* Schematic generated by S-Edit
* from file Design / module Cell / page Page
M2 Out A Gnd Gnd NMOS W='28*l' L='2*l' AS='148*l*l' AD='144*l*l' PS='68*l' PD='68*l' M=1
M1 Out A Vdd Vdd PMOS W='28*l' L='2*l' AS='148*l*l' AD='144*l*l' PS='68*l' PD='68*l' M=1
.ends
.subckt NOR2 A B Out Gnd Vdd
* S-Edit Info
* Designed by: Author Date
* Schematic generated by S-Edit
* from file Design / module Cell / page Page
M4 Out B Gnd Gnd NMOS W='28*l' L='2*l' AS='144*l*l' AD='84*l*l' PS='68*l' PD='34*l' M=1
M3 Out A Gnd Gnd NMOS W='28*l' L='2*l' AS='84*l*l' AD='144*l*l' PS='34*l' PD='68*l' M=1
M2 Out B 1 Vdd PMOS W='28*l' L='2*l' AS='148*l*l' AD='84*l*l' PS='68*l' PD='34*l' M=1
M1 1 A Vdd Vdd PMOS W='28*l' L='2*l' AS='84*l*l' AD='144*l*l' PS='34*l' PD='68*l' M=1
.ends
.subckt Non_Overlapping_Clock Clk O1 O2 Gnd Vdd
XInv_1 O1 N_1 Gnd Vdd Inv
XInv_2 N_1 N_2 Gnd Vdd Inv
XInv_3 O2 N_3 Gnd Vdd Inv
XInv_4 N_3 N_4 Gnd Vdd Inv
XInv_5 Clk N_5 Gnd Vdd Inv
XNOR2_1 Clk N_4 O1 Gnd Vdd NOR2
XNOR2_2 N_2 N_5 O2 Gnd Vdd NOR2
.ends
********* Simulation Settings - Parameters and SPICE Options *********
XNon_Overlapping_Clock_1 N_1 phi1 phi2 Gnd Vdd Non_Overlapping_Clock
vSource_v_pulse_1 N_1 Gnd pulse(0.0 5.0 0 1p 1p 500n 1000n)
vSource_v_dc_1 Vdd Gnd 5.0
********* Simulation Settings - Analysis section *********
.tran 100n 3u
********* Simulation Settings - Additional SPICE commands *********
.print vin vout vout2
.print phi1 phi2
.param l=1u
.end
RC-Low Pass Filter
Objective: Design a simple swiched capacitor RC low-pass filter with NMOS switches with
W=50um and L=2um. Cs=10pF and a load capacitance Cl=100pF. Use a fs=1MHz.
Rs will be 1/(10p * 1M) = 100kOhm
The circuit was connected as shown:
Here Vout is our output from the SCC and Vout2 is the output from an equivalent RC circuit
with resistance 100kOhm
This produces an output as shown:
The constant line is the Requ circuit and the steps show the SCC circuit output. We can see that
the SCC circuit simulates the RC circuit.
Tau (the time constant) can be seen here as 12.09us.
It can be calculated as Tau = (100k * 100p) = 10us
These Tau’s are roughly equivalent and both circuits can be assumed the same.
*************** Subcircuits *****************
.subckt Inv A Out Gnd Vdd
* S-Edit Info
* Designed by: Author Date
* Schematic generated by S-Edit
* from file Design / module Cell / page Page
M2 Out A Gnd Gnd NMOS W='28*l' L='2*l' AS='148*l*l' AD='144*l*l' PS='68*l' PD='68*l' M=1
M1 Out A Vdd Vdd PMOS W='28*l' L='2*l' AS='148*l*l' AD='144*l*l' PS='68*l' PD='68*l' M=1
.ends
.subckt NOR2 A B Out Gnd Vdd
* S-Edit Info
* Designed by: Author Date
* Schematic generated by S-Edit
* from file Design / module Cell / page Page
M4 Out B Gnd Gnd NMOS W='28*l' L='2*l' AS='144*l*l' AD='84*l*l' PS='68*l' PD='34*l' M=1
M3 Out A Gnd Gnd NMOS W='28*l' L='2*l' AS='84*l*l' AD='144*l*l' PS='34*l' PD='68*l' M=1
M2 Out B 1 Vdd PMOS W='28*l' L='2*l' AS='148*l*l' AD='84*l*l' PS='68*l' PD='34*l' M=1
M1 1 A Vdd Vdd PMOS W='28*l' L='2*l' AS='84*l*l' AD='144*l*l' PS='34*l' PD='68*l' M=1
.ends
.subckt Non_Overlapping_Clock Clk O1 O2 Gnd Vdd
XInv_1 O1 N_1 Gnd Vdd Inv
XInv_2 N_1 N_2 Gnd Vdd Inv
XInv_3 O2 N_3 Gnd Vdd Inv
XInv_4 N_3 N_4 Gnd Vdd Inv
XInv_5 Clk N_5 Gnd Vdd Inv
XNOR2_1 Clk N_4 O1 Gnd Vdd NOR2
XNOR2_2 N_2 N_5 O2 Gnd Vdd NOR2
.ends
********* Simulation Settings - Parameters and SPICE Options *********
XNon_Overlapping_Clock_1 N_1 phi1 phi2 Gnd Vdd Non_Overlapping_Clock
vSource_v_pulse_1 N_1 Gnd pulse(0.0 5.0 0 1p 1p 500n 1000n)
vSource_v_dc_1 Vdd Gnd 5.0
MMOSFET_N_1 N_2 phi1 Vin Gnd NMOS L=2u W=50u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_2 Vout phi2 N_2 Gnd NMOS L=2u W=50u AD=66p PD=24u AS=66p PS=24u
CCapacitor_1 N_2 Gnd 10pF
CCapacitor_2 Vout Gnd 100pF
vSource_v_pulse_2 Vin Gnd pulse(0.0 2.5 0 1n 1n 100 200)
RResistor_1 Vout2 Vin 100k TC=0.0, 0.0
CCapacitor_3 Vout2 Gnd 100pF
********* Simulation Settings - Analysis section *********
.tran 100n 40u
********* Simulation Settings - Additional SPICE commands *********
.print vin vout vout2
.param l=1u
.end
RC-Low Pass Filter II
Objective: Find the clock frequency (fs) required to produce a filter pole at 50kHz.
From the formulae above we can see that fs = (2 * pi * Cl * fp) / Cs
Thus:
fs = (2 * pi * 100p * 50k) / 10p = 3.14 MHz
For fs = 3.14 MHz we need a pulse time of 1 / 3.14M = 318ns
This gives a high time = low time = 159ns
This gives:
Rs = 1 / (10p * 3.14M) = 31.84kOhm
This circuit can be shown as:
This gives the following output:
It can be observed that the Tau in this circuit (3.84ns) is less than the tau in the previous circuit
(12ns). This is expected as Tau = (Rs * Cl). Thus, decreasing Rs will decrease Tau.
RC-Low Pass Filter III
Objective: To observe the equivalent resistance variation as fs varies between 1MHz, 5MHz
and 10MHz.
From above it can be observed that as fs=1MHz the Rs will be 100kOhm and the Tau will be
12.09us
For fs = 5MHz we will have a Rs = 20kOhm
This gives an output as shown:
The tau here is observed as 2.39us
And calculated as: Tau = (20k * 100p) = 2us
For fs = 10MHz we will have a Rs = 10kOhm
This gives an outpus as follows:
The tau here is observed as 1.21us
And calculated as: Tau = (10k * 100p) = 1us
Plotting the change in Rs with fs we obtain the following:
We can see as the frequency fs increases, the equivalent resistance (Rs) decreases. This is
expected since Rs is inversely proportional to fs.
Rs = 1 / (fs * Cs)
RC-Low Pass Filter IV
Objective: To observe the time constant variation as Cs varies between 5pF, 10pF and 20pF. Fs
is kept constant at 1MHz (Thus Rs = 100kOhm) and Cl = 100pF
Plotting the change in Rs with Cs the following can be seen:
(As Cs increases, Rs decreases)
Thus the time constant (tau) can be measured in each case:
( tau = Rs * Cl)
For Cs = 5pF: tau = (200k * 100p) = 20us
For Cs = 10pF: tau = (100k * 100p) = 10us
For Cs = 20pF: tau = (50k * 100p) = 5us
The circuit for Cs = 5pF would be set up as follows:
And produces the following output:
This circuit has a tau of 22.94us
The calculated tau was 20us
0 5 10 15 20 25 30 35 40
Time (us)
0.0
0.5
1.0
1.5
2.0
2.5
Volta
ge
(V)
v(vout2)
1.71
v(vout)
1.66
v(vin)
2.50
x1= x2= dx=22.94u 39.96u 17.02u y1= y2= dy=1.68 -10.18m -1.69Part_II.3
The circuit of Cs = 10pF would be set up as follows:
It produces the following output:
The measured tau for this circuit is 11.95us
The calculated tau was 10us
The circuit for Cs =20pF would be:
This circuit produces the following output:
The measured tau for this circuit is 5.95us
The calculated tau was 5us
If these results are plotted as capacitance against tau we obtain the following:
We can see that as we increase Cs, we decrease tau. This is expected since we are decreasing Rs
and tau is proportional to Rs (thus, tau is inversely proportional to Cs).
SCC-Integrator
Objective: To implement the SCC as a resistor in an ideal integrator using a VCVS (Voltage
Controlled Voltage Source). Fs=1MHz, Cs=10pF, (Rs = 100kOhm), VCVS gain = 120dB, Cf = 20pF
(feedback capacitor). Our voltage source will have a period of 20us, amplitude of 0.5V.
The circuit would be set up as shown:
This produces the following output:
0 10 20 30 40 50 60 70 80 90 100
Time (us)
-12
-11
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
Voltag
e(V
)
v(vout2)
v(vout)
v(vin)
Part_III
We can see that this is output follows the ideal integrater using Rs=100kOhm. We can also see
that the circuit is acting as an integrator since the output is summing up the input when there is
a signal on the input. It can be observed that the integrator is inverting because the output is a
negative voltage and the input is a positive input.
Zooming in on ½ a cycle shows the following:
The gain (K) of the circuit can be measured as follows:
K = (Voltage at point B) / (Area enclosed by A)
After ½ a cycle (10us) the area enclosed by A = (0.5 * 10u) = 5uVs
At this time, the voltage at point B = -2.5V
Thus; K = (-2.5 / 5u) = -500,000
(It is easy to see that this is inverting at this point since the K value is negative)
Calculated K = -1 / (Rs * Cf) = -1 / (100k * 20p) = -500,000
Netlist:
*************** Subcircuits *****************
.subckt Inv A Out Gnd Vdd
* S-Edit Info
* Designed by: Author Date
* Schematic generated by S-Edit
* from file Design / module Cell / page Page
M2 Out A Gnd Gnd NMOS W='28*l' L='2*l' AS='148*l*l' AD='144*l*l' PS='68*l' PD='68*l' M=1
M1 Out A Vdd Vdd PMOS W='28*l' L='2*l' AS='148*l*l' AD='144*l*l' PS='68*l' PD='68*l' M=1
.ends
.subckt NOR2 A B Out Gnd Vdd
* S-Edit Info
* Designed by: Author Date
* Schematic generated by S-Edit
* from file Design / module Cell / page Page
M4 Out B Gnd Gnd NMOS W='28*l' L='2*l' AS='144*l*l' AD='84*l*l' PS='68*l' PD='34*l' M=1
M3 Out A Gnd Gnd NMOS W='28*l' L='2*l' AS='84*l*l' AD='144*l*l' PS='34*l' PD='68*l' M=1
M2 Out B 1 Vdd PMOS W='28*l' L='2*l' AS='148*l*l' AD='84*l*l' PS='68*l' PD='34*l' M=1
M1 1 A Vdd Vdd PMOS W='28*l' L='2*l' AS='84*l*l' AD='144*l*l' PS='34*l' PD='68*l' M=1
.ends
.subckt Non_Overlapping_Clock Clk O1 O2 Gnd Vdd
XInv_1 O1 N_1 Gnd Vdd Inv
XInv_2 N_1 N_2 Gnd Vdd Inv
XInv_3 O2 N_3 Gnd Vdd Inv
XInv_4 N_3 N_4 Gnd Vdd Inv
XInv_5 Clk N_5 Gnd Vdd Inv
XNOR2_1 Clk N_4 O1 Gnd Vdd NOR2
XNOR2_2 N_2 N_5 O2 Gnd Vdd NOR2
.ends
********* Simulation Settings - Parameters and SPICE Options *********
XNon_Overlapping_Clock_1 N_1 phi1 phi2 Gnd Vdd Non_Overlapping_Clock
vSource_v_pulse_1 N_1 Gnd pulse(0.0 5.0 0 1p 1p 500n 1000n)
vSource_v_dc_1 Vdd Gnd 5.0
MMOSFET_N_1 N20 phi1 Vin Gnd NMOS L=2u W=50u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_2 N6 phi2 N20 Gnd NMOS L=2u W=50u AD=66p PD=24u AS=66p PS=24u
CCapacitor_1 N20 Gnd 10pF
CCapacitor_2 Vout N6 20pF
vSource_v_pulse_2 Vin Gnd pulse(0 0.5 0 1n 1n 10u 20u)
RResistor_1 N8 Vin 100k TC=0.0, 0.0
CCapacitor_3 Vout2 N8 20pF
eVCVS_1 Vout Gnd Gnd N6 1000000
eVCVS_2 Vout2 Gnd Gnd N8 1000000
********* Simulation Settings - Analysis section *********
.tran 1u 100u
********* Simulation Settings - Additional SPICE commands *********
.print vin vout vout2
.param l=1u
.end