Post on 29-Dec-2015
K&H MFG. Co., LTD. Manufacturer, Exporter & Importer for Educational Equipment & Measuring Instrument
CIC-310CPLD/FPGA Development System
CIC-310 CPLD/FPGA Development System
§ Hardware Overview --- System Overview --- Development Board --- Experiment Board
§ Design Flowchart --- Experiment Flowchart --- Programming Flowchart --- Program manager
§ Experiments --- List of experiments --- Implementations
§ CPLD / FPGA Background
CIC-310 CPLD/FPGA Development System
§ Hardware Overview --- System Overview --- Development Board --- Experiment Board
§ Design Flowchart --- Experiment Flowchart --- Programming Flowchart --- Program manager
§ Experiments --- List of experiments --- Implementations
§ CPLD / FPGA Background
Traditional design flow of the logic circuit
In = A, B, C, D ...Out = X, Y …
Designspecification
Truth table
Manual
X = (Ā+B+C) (B+D) ( Ā+D )Booleanexpression
Manual (K-map)
§ CPLD/FPGA BACKGROUND – (1)
Implement onseveral ICs
Manual
PAL – Programmable Array Logic Programmable AND array followed by fixed fan-in OR gates
CBACBAf 1
A B C
AND plane
Programmable switch or fuse
PLD - Programmable Logic Device
A B C
AND plane
PLD
D Q
Q
S0S1
B
DC
AQ
HDL : Hardware Description Language
CPLD (Complex PLD) StructureIntegration of several PLD blocks with a programmable interconnect on a single chip
PLDBlockPLD
BlockPLD
BlockPLD
Block
Interconnection MatrixInterconnection Matrix
I/O B
lock
I/O B
lock
I/O B
lock
I/O B
lock
PLDBlockPLD
BlockPLD
BlockPLD
Block
I/O B
lock
I/O B
lock
I/O B
lock
I/O B
lock
• • •
Interconnection MatrixInterconnection Matrix
• • •
• • •
• • •
FPGA Look-Up Tables (LUT)• Look-up table with N-inputs can be used to implement
any combinatorial function of N inputs• LUT is programmed with the truth-table
LUTLUT
ABCD
Z
A
B
C
D
Z
Truth-table Gate implementation
LUT implementation
• FPGAs vs. CPLDs
• Are FPGAs and CPLDs the same thing? No. Both are programmable digital logic chips. Both are made by the same companies. But they have different characteristics.
• FPGAs are "fine-grain" devices. That means that they contain a lot (up to 100000) of tiny blocks of logic with flip-flops. CPLDs are "coarse-grain" devices. They contain relatively few (a few 100's max) large blocks of logic with flip-flops.
• FPGAs are RAM based. They need to be "downloaded" (configured) at each power-up. CPLDs are EEPROM based. They are active at power-up (i.e. as long as they've been programmed at least once...).
• CPLDs have a faster input-to-output timings than FPGAs (because of their coarse-grain architecture, one block of logic can hold a big equation), so are better suited for microprocessor decoding logic for example than FPGAs.
• FPGAs have special routing resources to implement efficiently binary counters and arithmetic functions (adders, comparators...). CPLDs do not.
• FPGAs can contain very large digital designs, while CPLDs can contain small designs only.
FPGA & CPLD
• FPGAs are RAM based. They need to be "downloaded" (configured) at each power-up. CPLDs are EEPROM based. They are active at power-up (i.e. as long as they've been programmed at least once...).
• FPGAs can contain very large digital designs, while CPLDs can contain small designs only.
• CPLDs have a faster input-to-output timings
Modern design flow of the logic circuit
Designspecification
In = A, B, C, D ...Out = X, Y …
Implement on ONECPLD/FPGA chip
Automatic
Design description
HDL Syntax
Manual(programming) Save lots of time!!!
§ CPLD/FPGA BACKGROUND – (2)
FPGA/CPLDFPGA/CPLD
CounterCounter
ConverterConverter
TimerTimer
PWMPWM
MPUMPU
GPIOControl
GPIOControl
DecoderDecoder
MCUMCU
MemoryMemory
ALUALU
SOPC (System On Programmable Chip)
CIC-310 CPLD/FPGA Development System
§ Hardware Overview --- System Overview --- Development Board --- Experiment Board
§ Design Flowchart --- Experiment Flowchart --- Programming Flowchart --- Program manager
§ Experiments --- List of experiments --- Implementations
§ CPLD / FPGA Background
§ System Overview
CIC-310 provides digital system designers with an economical solution for hardware verification or students with an efficient learning of digital system design.
CPLD/FPGA Development Board
Experiment Board+CIC-310 =
Altera 8k/10kRAM-based FPGA RS232 connector
Max. 32kB SEEPROM7.5C DC Power
89C2051 for load the configuration data to FPGA or SEEPROM devices with data compression techniques
HIN230 for RS-232 transmitters/receiversinterface circuits
Reset button:Reset connection to PC
Program selector jumper 11.0592MHz Xosc
§ Hardware Overview – Development Board
Logic Switch Input Section
Input Status Logic LED Display
Output Logic LED Display
20MHz X’TRAL OSC
6-Digit Parallel-Serial 7-segment Display
RC Oscillator
Pulse generator SW and Keypad Section
5 x 7 DOT LED display
16-Segment Display Section
§ Hardware Overview – Experiment Board
CIC-310 CPLD/FPGA Development System
§ Hardware Overview --- System Overview --- Development Board --- Experiment Board
§ Design Flowchart --- Experiment Flowchart --- Programming Flowchart --- Program manager
§ Experiments --- List of experiments --- Implementations
§ CPLD / FPGA Background
§ EXPERIMENT FLOWCHART
PersonalComputer
Development Board
Rs-232
Programming
Download the program
Windows 98/2000/XP
Experiment Board
Show theresult
Program manager
Download the program to FPGA and execute the program
Add the program to SEEPROM
Execute the program from SEEPROM
§ Program manager functions
CIC-310 CPLD/FPGA Development System
§ Hardware Overview --- System Overview --- Development Board --- Experiment Board
§ Design Flowchart --- Experiment Flowchart --- Programming Flowchart --- Program manager
§ Experiments --- List of experiments --- Implementations
§ CPLD / FPGA Background
§ LIST OF EXPERIMENTS
• Combinational logic circuits– Applications of ALUs
– Encoder / Decoder
– Alpha-Nemaric LED display
– Multiplexer / Demultiplexer
• Sequential logic circuits– Flip-flop circuits
– Applications of counters
– Frequency synthesizers / Shift Registers
• Dynamic 5x7 LED matrix display• 4x4 keypad of matrixes
More than 50 examples in the experimental manual!!!
Implementations
Exp1 : Step by step design of basic logic circuit by Graphic and Text Editor
Exp2 : Binary-to-16-segment decoder
Exp3: Counters
Exp4: 5X7 DOT matrix display
Exp5: Keypad
Input: P01, P02, P03, P04, P06, P07, P08
Output : P55, P56, P57, P58
Exp1: Basic logic circuit design (Primal.gdf)
Specification:
Input: DIP switchesOutput: LED display
Relation:P55 = !P01P56 = P02 & P03P57 = P04 # P06 P58 = P07 $ P08
! => NOT& => AND# => OR$ => XOR
Step 5: Download the program
Download the program to FPGA and execute the program
Add the program to SEEPROM
Execute the program from SEEPROM
Exp2: Binary-to-16-segment decoder
Specification:
Input: DIP switchesOutput: 16-segment display
Relation:6 bit inputs are decoded to 16-segment display as:
Numerical number : 0~9Alphabet letters : A~Z Math Operators: * , +,-,/
Why you need 6-bit input? Input: P01, P02, P03, P04, P06, P07
Output : 16-segment display
0~9 10A~Z 26 * ,+,-,/ 4
10+26+4=40 2^6 = 64 > 40
Program by Text Editor --- 16segb.tdf
.
.
.
a1 a2 b1 b2 c1 c2 d1 d2 e1 e2 g1 g2 h1 h2 i1 i2 /p
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Symbol
Position
16-segment
FPGA
8K 10k16-
segmentFPGA
8K 10k
A1 P13 P16 E2 P23 P27
A2 P14 P17 G1 P24 P28
B1 P15 P18 G2 P25 P29
B2 P16 P19 H1 P27 P30
C1 P18 P21 H2 P28 P35
C2 P19 P22 I1 P29 P36
D1 P20 P23 I2 P30 P37
D2 P21 P24 DP P63 P64
E1 P22 P25 C-SEL P23 P27
Table 1-6 16 segment display pin-out (8k-84pin)
1
2
Pin Assignment (1)
P13 P14
P15
P16
P18P19
P20
P21
P22 P23
P24
P25
P27
P28
P29
P30
P63
a1 a2 b1 b2 c1 c2 d1 d2 e1 e2 g1 g2 h1 h2 i1 i2 /p
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
13 14 15 16 18 19 20 21 22 23 24 25 27 28 29 30 63
SymbolSegment
Pin
Pin Assignment (2)
Show Result
16 17 18 19 21 22 23 24 25 27 28 28 30 35 36 37 64
a1 a2 b1 b2 c1 c2 d1 d2 e1 e2 g1 g2 h1 h2 i1 i2 /pSymbolFPGA Pin
FPGA
JP8 JP9 JP10
JP8 JP9 JP10
Exp3: Counters
Specification:
Input: Enable: Sw1_1 Reset: Sw1_2 Clock: SWP3
Output: LED display
Relation:The 4-bit ripple counter repeats itself for every 2^4 (16) clock pulses. :
Input: Sw1_1, p01 (Enable) Sw1_2, P02 (Reset) SWP3, P83 (Clock)
Output : P55, P56, P57, P58
Construct a 4-bit asynchronous counter by T flip-flops
4 Digit Counter: Frequency Counter --- pdec9999.tdf
Input: ClockOutput: LED Display (Counting 0~9999 in binary format)
SA SB SC SD SE SF SG
7 segment displayer --- 7segd.tdf
Input: DIP switch
Output: 7 segment displayer
4 Digit Counter: Parallel mode --- 4dec7sp.tdf
Require Pins: 6 x 4 = 24
0 1 2 3 4 5 76 8 9 0 1 2 3 4 5 76 8 90 1 2 3 4 5 76 8 9
PA1
PA2
PA3
PA7
PA6
PA4
PA5
P13
P14
P15
P20
P19
P16
P18
P22P23P24P25P27
5x7 Matrix DOT display (dot_test.tdf)
Exp4: 5x7 dot matrix display
5x7 DOT Matrix display (dot_test.tdf)
PA1
PA2
PA3
PA7
PA6
PA4
PA5
P13
P14
P15
P20
P19
P16
P18
P22 P23 P24 P25 P27
TRY 57dots.hex !!!
1010101
Counter
Individual Mode --- require 16 ports
Scan Mode --- require 8 ports
P34
P35
P36
P37
P39
P40
P41
P42
P43
P44
P45
P46
P48
P49
P50
P51
Parallel Mode => PKI1, PKI2, PKI3Serial Mode => SCN1, SCN2, SCN3
Exp5: Keypad
C: Keypad Circuit Design with debounce function --- Parallel Mode (16_KEY_Parallel.tdf)
Parallel Mode => PKI1, PKI2, PKI3Serial Mode => SCN1, SCN2, SCN3
D: Keypad Circuit Design with debounce function --- Scan Mode (16_key_scan.tdf)
Parallel Mode => PKI1, PKI2, PKI3Serial Mode => SCN1, SCN2, SCN3