Post on 02-Feb-2018
Jitter vs SNR for ADCsTIPL 4704
Created by Thomas NeuPresented by Thomas Neu
1
Sampling TheoryHigh-speed ADC uses external clock input to sample the analog input signal.
Higher input frequencies are more susceptible to timing uncertainty
Sampling Clock JitterSampling jitter is combination of:• External jitter• Internal ADC aperture jitter
2_2
, ADCApertureextJitterJitter TTT
ADC Aperture JitterClock amplitude dependent
SNR Impact of Jitter (1)The ADC SNR degradation due to jitter (external + internal ADC aperture) can be calculated as:
)2log(20 JitterinJitter TfdBcSNR
50
60
70
80
90
100
110
10 100 1000
Fin (MHz)
SNR
(dB
c)
0.05 ps0.1 ps0.2 ps0.4ps
SNR Impact of Jitter (2)The ADC noise floor (SNR) is basically set by 3 different contributors:1. ADC Quantization Noise2. ADC Thermal Noise3. Jitter degradation
2
20
2
20
2
20 101010log20
JitterNoiseThermalNoiseinQuantizatoSNRSNRSNR
ADC dBcSNR
50
60
70
80
90
100
10 100 1000
Fin (MHz)
SNR
(dB
c)
Calculating the jitter magnitude (1)The clock jitter is calculated by integrating the phase noise of the clock signal.
Lower integration limit:Typically application specific.
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Offset Frequency (Hz)
500Hz to 40MHzTj = 50fs
60Hz to 40MHzTj = 350fs
Clock Frequency = 122.88MHz
Calculating the jitter magnitude (2)Upper integration limit:The upper limit is set by factors like • Clock filter bandwidth• ADC clock input bandwidth• ADC sampling rate
ADS54RF63 @ Fin = 1GHz, Fs = 122.88Msps with added noise on clock input
-120
-100
-80
-60
-40
-20
0
0 10 20 30 40 50 60
No LPF300MHz LPF100MHz LPF1MHz LPF
Clock Frequency = 122.88MHz
SNR impact in frequency domain During the sampling process the clock signal phase noise gets added to the input signal. • The higher the input signal the larger the phase noise amplitude (scales by 20log (FIN/FS))• The larger (worse) the clock phase noise, the worse the ADC noise floor degradation
ADC thermal noise
Clock jitter (phase noise)
Input signal
Higher input frequency & larger jitter amount
Why is clock jitter/phase noise so critical?A typical receiver use case is performance in a ‘blocking condition’ • The receiver needs to detect a small wanted signal• There is a large in-band interferer that can’t be filtered out.
ADC thermal noise
Wanted Signal Interferer
Clock Phase Noise
How to maximize the jitter performance?There are several steps the system designer can take in order to maximize the SNR performance of a given ADC:• Use low jitter/phase noise clock source• Use bandpass filter with low insertion loss to limit broad band noise degradation• Ensure clock amplitude is sufficient and doesn’t degrade ADC aperture jitter
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