Post on 04-Feb-2016
description
International Center on Design for Nanotechnologies(IC-DFN)
Jason CongUniversity of California, Los Angeles
Tel: 310-206-2775, Email: cong@cs.ucla.edu
(Other participants are listed inside)
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Project Summary
• Establish an International Center on Design for Nanotechnologies (IC-DFN)
• Project focus
– Design methodologies
– Systems-level issues
– International collaboration to leverage global investment and coordinate research
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Current Research Team US
UCLA: Jason Cong (Center co-director) and Kang Wang UC Santa Barbara: Tim Cheng (Center co-director) and Evelyn Hu
Taiwan National Tsinghua University (NTHU): Shih-Chieh Chang (Taiwan
coordinator) Cheng Chung Chi, Shi-Yu Huang, Tingting Hwang, Youn-Long Lin, C. L. Liu, Cheng-Wen Wu
National Taiwan University (NTU): Yao-Wen Chang, Juin-Lang Huang, Chien-Mo Li, Ric Huang
China Tsinghua University (THU): Jinian Bian, Xianlong Hong (China
coordinator) Peking University (PKU): Xu Cheng, Ru Huang Zhejiang University (ZJU): Xiaolang Yan, Zhizhen Ye
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Division of Research and Educational Tasks
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Research Overview
• Thrust 1: Technology and Architecture/Platform Driver– Technology Driver– Architecture/Platform Driver:nano-FPGA
• Thrust 2: Design for Nano-Technology
– Design for Robustness– Enable Higher Level of Abstraction
– Efficient Solutions to Fundamental Design Automation Problems
• Thrust 3: Design/Application Driver
– Multi-Core Heterogeneous SOC Design in Nanotechnologies
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Thrust 1(a): Technology Driver (Led by Kang Wang and Evelyn Hu)
– Technology characterization, in terms of reliability, process variation, etc. (UCSB, ZJU)
– Design of circuit blocks, e.g. memory cells, logic gates, and multiplexors (UCLA, PKU)
– Bottom-up assembly techniques (UCSB, NTHU)
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Thrust 1(b) –Architecture/Platform Driver:nano-FPGA (Led by Jason Cong and Kang Wang)
– Technology characterization, in terms of reliability, process variation, etc. (UCLA, UCSB, ZJU)
– Exploration of reconfiguration technologies (PKU and UCLA)
– Circuit-level design of nano-FPGA (PKU and UCLA)
– Logic-level design of nano-FPGA (UCLA and NTHU)
– Basic design flow for mapping gate-level circuits to nano-FPGAs (UCLA, NTU and THU)
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Thrust 2(a) – Design for Robustness (Led by Tim Cheng)
– Exploring tradeoffs between reconfiguration and redundancy for reliable design (UCSB)
– On-line/off-line self-test and self-diagnosis to support reconfiguration (UCSB)
– Architectural design for timing-error-tolerance (NTHU, NTU, and UCSB)
– Functional error tolerance for nano-FPGA and nano-structured ASIC (NTHU)
– CAD issues on synthesis, mapping, and routing of reliable design with built-in reconfiguration and redundancy capabilities (NTHU, NTU, and ZJU)
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Thrust 2(b) – Enable Higher Level of Abstraction(Led by Jason Cong)
• System-level performance modeling and estimation (UCLA)
• System-level and behavior-level synthesis (UCLA and THU)
• System-level and behavior-level property check and equivalence checking (UCSB)
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Thrust 2(c): Efficient Solutions to Fundamental Design Automation Problems
• Efficient high-level satisfiability checking (UCSB)
• Multilevel optimization (UCLA and NTU)
• Efficient solver for large-scale linear systems (THU and NTHU)
• Multi-space search and search space smoothing (THU)
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Thrust 3 – Design Driver(Led by Prof. Youn-Long Lin)
Multi-Core Heterogeneous SOC Design in Nanotechnologies
• CPU core designs (PKU), DSP core designs (ZJU), and video codec designs (NTHU)
• On-chip interconnect structure design (NTHU)
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Education(Led by Prof. Cheng, Prof. Hu and Prof. Cong)
• Semi-annual workshops (locations rotating among the U.S., mainland China and Taiwan)
• Web seminars
• Establishment of international internships
• Partnership with UC EAP program, joint activities with IPAM (UCLA) and CMS (ZJU)
• Providing seminars to WiSE and/or MESA and participate in CNSI’s INSET and EPSEM programs
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Focus of Years 1 & 2 (US Team)
• Thrust 1: Technology and Architecture/Platform Driver– Technology Driver– Architecture/Platform Driver:nano-FPGA
• Thrust 2: Design for Nano-Technology
– Design for Robustness– Enable Higher Level of Abstraction
– Efficient Solutions to Fundamental Design Automation Problems
• Thrust 3: Design/Application Driver
– Multi-Core Heterogeneous SOC Design in Nanotechnologies
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International Collaboration Activities
• Proposal planning meetings on Nov. 2004 (Hawaii) and Jan. 2005
(Shanghai)
• Proposal submitted to NSF in March 2005 and funded in October
2005
• 1st IC-DFN workshop in Jan. 2006, Huilian, Taiwan
• 2nd IC-DFN workshop in Aug. 2006, Hangzhou, China