Post on 03-Jan-2016
description
Index addressing (2)
• Advantages:- Allows specification of fixed offset to operand
address
• Disadvantages:- Extra addition to operand address
• Notation: ADD X(R1),R3 (X=number)• Meaning: [R3] [R3] + M([R1] + X)
Example index addressing
NE
Program with index addressing
programloop
sexagesalary
nEmpoyee IDsexagesalaryEmpoyee ID
L
Move #E,R0
Move N,R1
Clear R2
Add 8(R0),R2
Add #16,R0
Decrement R1
Branch>0 L
Div R1,R2
Move R2,Sum
Move N,R1
0(R0) 4(R0) 8(R0)12(R0)16(R0)20(R0)
Q1: What does this program do?
Additional modes
• Some computers have auto-increment (decrement instructions)
• Example: (R0)+• Meaning .. M(R0)..; [R0] [R0]+1• Example: -(R0)• Meaning [R0] [R0]-1; .. M(R0)..
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Additional Instructions
• Logic instructions- Not R0; invert all bits in R0- And #$FF000000,R0; AND with bit string
• Shift and rotate instructions- Many variants for different purposes
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Logical shifts
CR00
before:
after:
0
1
0 0 01 1 1 . . . 11
0 0 1 1 1 000
Logical shift leftLShiftL #2,R0
C R0 0
before:
after:
0
1
0 0 01 1 1 . . . 11
1 10 . . . 00101
. . .
used in bit Packing
virtual: 0 1 11 1 0 . . 010.
LShiftL #2,R0
LShiftL #1,R0
Logical shift rightLShiftR #2,R0
00 00 1 1 . . 101 .virtual:
LShiftR #2,R0
LShiftR #1,R0
8
Arithmetic shifts
C
before:
after:
0
1
1 1 00 0 1 . . . 01
1 1 0 0 1 011
R0
. . .01 11 0 0 . . 101 .virtual:
AShiftR #2,R0
AShiftR #1,R0
Arithmetic shift right (signed shift)AShiftR #2,R0
Q1: AShiftR by n bits is equivalent to division by 2n for numbers in 2C or 1C?Q2: Rounding negative number shifts towards 0 or -infinity?T
ough
qu
estio
ns
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Rotate
Rotate left w/o CarryRotateL #2,R0
C R0
before:
after:
0
1
0 0 01 1 1 . . . 11
1 10 . . . 10101
virtual: 0 1 11 1 0 . . 010.
RotateL #2,R0
RotateL #1,R0
Rotate left w/ CarryRotateLC #2,R0
C R0
before:
after:
0
1
0 0 01 1 1 . . . 11
1 10 . . . 00101
virtual: 0 1 11 1 0 . . 010.
RotateLC #2,R0
RotateLC #1,R0
Done so far…
Circuit Design
Digital logicMemory elementsOther building blocks (Multiplexer,Decoder)Finite State Machines
Lecture 1
Programmable Devices
Memory organizationProgram sequencingvon Neumann archi.Instruction levels
Lecture 2
History of Computing(1642-2011)
Why Computer Organization Matters?Lecture 0
ComputersLectures 3,4
Data representation, conversion, and op.Instruction representation and use
Problem: How to Program Computers?
Circuit Design
Digital logicMemory elementsOther building blocks (Multiplexer,Decoder)Finite State Machines
Lecture 1
Programmable Devices
Memory organizationProgram sequencingvon Neumann archi.Instruction levels
Lecture 2
Why Computer Organization Matters?Lecture 0
ComputersLectures 3,4
Data representation, conversion, and op.Instruction representation and use
TU-DelftTI1400/11-PDS
13
Program Creation and Execution Flow
editor
type sourceprogram
Source in ASCII
linker/loaderlink/load
memory imagerun input/output
machine 2
assembler listingtranslate
Source andObject code+error messages
object code
machine 1
Three levels of instructions
fetch/executeimplementation
program executionin hardware
high level programminglanguage
program expressed in ahigh-level language
translation
instruction set program expressed as a series of instructions
direct implementationAssembler
C/C++, Java, …
15
Instructions and Addressing
1. Introduction2. Assembler: What and Why?3. Assembler Statements and Structure4. The Stack5. Subroutines6. Architectures: CISC and RISC
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16
Why assembler? [1/2]
• Assembler is a symbolic notation for machine language
• It improves readability (vs machine code):- Assembler: Move R0,SUM - Machine code: 0010 1101 1001 0001 (16 bits)
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Why assembler ? [2/2]
• Speed of programs in critical applications• Access to all hardware resources of the
machine• Target for compilers
Source: http://www.cs.berkeley.edu/~volkov/cs267.sp09/hw1/results/
Lecture 0
Q: Where to get ISA references?
• Manufacturer’s documentation
• Third-party manuals (ATTN: may be incorrect)
Q: Does each processor have its own machine language (instruction set)?• Shared across generations and even
competitors
www.eng.ucy.ac.cy/theocharides/Courses/ECE656/ia-32.pdf
developer.download.nvidia.com/compute/cuda/3_1/toolkit/docs/ptx_isa_2.1.pdf
1982
1985
1989
1993
1995
Intel
AMD
Cyrix
…
NVIDIA
Q: Are similar instructions identical on different platforms?• Often, they are not
NVIDIAIntel
AMD
Cyrix
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21
Machine Language [1/4]
• Is Machine language difficult to learn?- That holds for every unknown language. Machine
language is more difficult because you have to work with the specifically defined micro instruction set.
• Is Machine language difficult to read and to understand?- Of course, if you do not know the language;
however, assembler is more difficult to read and understand than a High Level Language (HLL).
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Machine Language [2/4]
• Is Machine language difficult to write?- Often HLL languages use libraries to make programming
simpler. Machine language programmers often start from scratch. However, full performance may require machine language implementation (or a smart/expensive compiler)
• Machine language programming is time consuming- One estimates that the time for coding a program is only
30% of the total development time.
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Machine Language [3/4]
• Compilers make machine language superfluous- A good machine language program often looks very
different from a compiler generated program. Generally, a C program will win over a hand-made assembly program (unless you’re Michael Abrash … or a student at TU Delft)
- Assembler still heavily used for hot/optimized functions (esp. scientific codes), real-time platforms, embedded systems, …
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Machine Language [4/4]
• Is Machine language difficult to maintain?- Maintainable programs are not specifically dependent on
the language they are written in, but more on the way they are contructed
• Is Machine language difficult to debug?- Often debuggers output both the HLL and the machine
language, and the error can only be found in the generated machine language
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Case
Universele Brander AutomaatKlant: Nefit Fasto B.V.Markt: HVAC (AirCo)Ontwikkelen (1990) en produceren (100k/jaar) van de UBA universele brander- automaat voor Nefit Fasto voorzien van een bipolaire Application-Specific Integrated Circuit (ASIC).Eerste product met een universeel karakter, die een fail-safe approval heeft.
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Case
6 schakel ingangen8 analoge ingangen3 schakeluitgangen3 modulerende uitgangen2 draads communicatie bus
Externe KIM module aansluiting met 178 bytes config settings
230V , Pump and Fan
ASIC and micro-Computer
Ignition
Universele Brander Automaat
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UBA micro computer
HWIO
1 Kbytes
MC68HC05B16
24 I/O bi-directional8 A/D analogue inputs2 TCAP input timers2 TCMP output compare2 PWM D/A outputs1 SCI serial output 1 COP watchdog256 bytes RAM256 bytes EEPROM16 Kbytes (EP)ROM
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UBA PuR After Power up Reset special routine[ see also The Zen of Diagnostics, http://www.ganssle.com/articles/adiags1.htm ]
- all instruction set in test routine- 16-bit CRC (99,98% data integrity)
- Walking A0 and 05 RAM test (pattern sensitivity)- Check on A/D (converter linearity)
- Main loop partitioned in modules- Module check in each phase
- Acknowledge module check by pulse to ASIC (350ms)- Interrupt program termination check by pulse to ASIC (20ms)
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UBA Assembly
• Check instruction set- Test of each opcode over and over
again- Emergency stop at fault detection- Not possible in “C”
• Check memory- As part of the program- Emergency stop at fault detection- Difficult in “C”
• Better control on application- Compiler generated code must be
checked for correctness.
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Instructions and Addressing
1. Introduction2. Assembler: What and Why?3. Assembler Statements and Structure4. The Stack5. Subroutines6. Architectures: CISC and RISC
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Assembler Statements
• Declarations- no code generation- memory reservation- symbolic data declarations- where to start the code execution
• Executable statements- are translated to real machine instructions
(often, one-to-one)
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Data declarations
S EQU 200
ORIGIN 201
N DATA 300
N1 RESERVE 300
ORIGIN 100
Label operation operand
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Program
START Move N,R1
Addr operation operand
Move #N1,R2
Clear R0
LOOP Add (R2),R0
Incr R2
Decr R1
Branch>0 LOOP
Move R0,S
Return
End START
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Memory lay-out
Move N,R1100
..... 102
103
104
105
106
107
101
..... ..... ..... ..... Branch >0
200
300 202
203
501
201
..... ..... ..... .....
Nn
S
N
N1
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Structure assembler [1/3]
• Assembler is hardly more than substitution- substitute 0001 for Move- substitute 0000 0000 0000 0101 for #5
• Assembler is level above machine language• Assembler languages for different
architectures are alike, but not identical
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Structure assembler [2/3]
Assembler programs contain three kind of quantities:
• Absolute:- opcodes, contants: can be directly translated
• Relative:- addresses of instructions which are dependent of
final memory location
• Extern:- call to subroutines
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Structure assembler [3/3]
• Literals: constants in programs• Some assemblers act as if literals are
immediate operands• Example:
Load #1
is equivalent to:Load One
...
One: 1
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Number notation
• Numbers can be represented using various formats:
ADD #93,R1
orADD #%01011101,R1
orADD #$5D,R1
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Instructions and Addressing
1. Introduction2. Assembler: What and Why?3. Assembler Statements and Structure4. The Stack5. Subroutines6. Architectures: CISC and RISC
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The StackMain idea
- (Large?) Memory space used to store program data- Items are added to the stack through a PUSH operation- Items are removed from the stack through a POP
operation
Details- Often, a stack is a contiguous array of memory
locations- Often, any number of stacks can be set up by a
program- Often, only one stack can be used at a time
(changing the active stack possible at any time)Q1: Why use stacks?
Q2: Implications?
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Push
70
300
20
10
60
SP
Subtract #4,SPMove R0,(SP)
80
0
1
80 R0
or:Move R0,-(SP)
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Instructions and Addressing
1. Introduction2. Assembler: What and Why?3. Assembler Statements and Structure4. The Stack5. Subroutines6. Architectures: CISC and RISC
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Subroutines
• More structure in programs• Mimics procedure and function calls in
High Level programming Languages (HLL)
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Calling mechanism
Call SUB
next instr.
200
204
................1000
................
RTS
204
204
PC Link
PC Link
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Subroutine nesting
• For nesting of subroutines return address in link register must be stored
• Can be implemented by using stacks
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Subroutine stack
204
PC Link
Move Link, -(SP)
Stack
......
Move (SP)+, Link
RTS
subroutine
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Parameter passing (1)
• Through registers- fast- limited number of parameters- caller and callee must know where parameters
are placed
• Example:Move A,R0 Sub: Move R0,CCall Sub ......
RTS
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Parameter passing (2)
• Through memory- very flexible- slower than through registers
• Often implemented through Stack Pointer• Parameters are pushed on stack before
calling subroutine• Results are popped from stack after return• Subroutine needs registers
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Parameter passing (3)
Move #List, -(SP)Move N, -(SP)Call LISTADDMove 4(SP), SUMAdd #8, SP
calling subroutine
Stack
SP
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Parameter passing (3)
Move #List, -(SP)Move N, -(SP)Call LISTADDMove 4(SP), SUMAdd #8, SP
LISTSP
calling subroutine
Stack
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Parameter passing (3)
Move #List, -(SP)Move N, -(SP)Call LISTADDMove 4(SP), SUMAdd #8, SP
n
LIST
SP
calling subroutine
Stack
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Parameter passing (3)
Move #List, -(SP)Move N, -(SP)Call LISTADDMove 4(SP), SUMAdd #8, SP Return
n
LIST
SP
calling subroutine
Stack
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Parameter passing (3)
Move #List, -(SP)Move N, -(SP)Call LISTADDMove 4(SP), SUMAdd #8, SP
n
sum
SP
calling subroutine
Stack
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Parameter passing (3)
Move #List, -(SP)Move N, -(SP)Call LISTADDMove 4(SP), SUMAdd #8, SP
SP
calling subroutine
Stack
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Parameter passing (4)
[R0]
Return
n
LIST
Stack frameLISTADD Move R0, -(SP)...Move 16(SP), R1Move 20(SP), R2Clear R0
LOOP Add (R2), R0Decr R1Incr R2Branch>0 LOOPMove R0, 20(SP)Move (SP)+, R2.....Return
Subroutine
SP
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Parameter passing (4)
[R2]
[R1]
[R0]
Return
n
LIST
Stack frameLISTADD Move R0, -(SP)...Move 16(SP), R1Move 20(SP), R2Clear R0
LOOP Add (R2), R0Decr R1Incr R2Branch>0 LOOPMove R0, 20(SP)Move (SP)+, R2.....Return
Subroutine
SP
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Parameter passing (4)
[R2]
[R1]
[R0]
Return
n
sum
Stack frameLISTADD Move R0, -(SP)...Move 16(SP), R1Move 20(SP), R2Clear R0
LOOP Add (R2), R0Decr R1Incr R2Branch>0 LOOPMove R0, 20(SP)Move (SP)+, R2.....Return
Subroutine
SP 0(SP)
4(SP)
8(SP)
12(SP)
16(SP)
20(SP)20(SP)
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Parameter passing(4)
[R1]
[R0]
Return
n
sum
Stack frameLISTADD Move R0, -(SP)...Move 16(SP), R1Move 20(SP), R2Clear R0
LOOP Add (R2), R0Decr R1Incr R2Branch>0 LOOPMove R0, 20(SP)Move (SP)+, R2.....Return
Subroutine
SP
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Parameter passing (4)
Return
n
sum
Stack frameLISTADD Move R0, -(SP)...Move 16(SP), R1Move 20(SP), R2Clear R0
LOOP Add (R2), R0Decr R1Incr R2Branch>0 LOOPMove R0, 20(SP)Move (SP)+, R2.....Return
Subroutine
SP
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Frame Pointer
SP(stack pointer)
FP(frame pointer)
saved [R1]
saved [R0]
Stackframefor
calledsubroutine
Return address
localvar3
localvar2
localvar1
saved [FP]
Old ToS
param2
param1
param3
param4
(top-of-stack)
Access of local variablesof Subroutinethrough IndexAddressing on FP
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Re-entrancy
• Subroutines can be called more than once- Recursion: subroutine calls itself- Sub A calls Sub B, which in turn calls Sub A- Multiple callers “at the same time”
• Special measures for re-entrancy- No change of instructions- Each caller must have its own copy of data- Use stack(s)
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Instructions and Addressing
1. Introduction2. Assembler: What and Why?3. Assembler Statements and Structure4. The Stack5. Subroutines6. Architectures: CISC and RISC
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CISC characteristics
• Complex Instruction Set• Traditional architectures• Powerful instructions
- Complex operations- Many instructions
• Memory to memory operations• Programs often use stacks• Examples 68xxx and 80xxx architectures• The Pentium architecture
Memory CPU
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RISC characteristics
• Reduced Instruction Set• Small number of instructions• Load/Store from memory• Operations between registers• Large register sets• Example PowerPC architecture
Memory CPU
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Pro CISC
• Easier to program• Reduced code size• Complexity in hardware not in software
- HLL support in hardware
• (Politics) Legacy- CISCs are in all our PCs and servers
See also: http://arstechnica.com/cpu/4q99/risc-cisc/rvc-5.html
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Con CISC
• Instruction encoding complex• Variable number of cycles to load instruction
- IA-32 instructions can be 1—17 bytes long
• Many instructions too specific, thus not used• May be slow
- Stacks are in main memory, registers are near processor
• May consume more energy- Not in embedded systems, portable devices, …