IDESA CMOS Physics Using MASTAR Part 1of2x

CMOS Physics using MASTAR

(20 Tutorials containing 57 MASTAR exercises )(20 Tutorials containing 57 MASTAR exercises )

Thomas Skotnicki & Frederic Boeuf

Summary

� This set of slides intends to cover a wide part of the CMOS device physics from the basic solid-state properties to the system level functions, using the MASTAR software

� ~ 57 Exercices can be found within 20 Tutorials

T. Skotnicki & F. Boeuf

� ~ 57 Exercices can be found within 20 Tutorialscovering several aspects of the device and CMOS circuit physics and operation

Outline� Tutorial 1 : General MASTAR presentation (1 ex.)� Tutorial 2 : Creating a Profile (Saving device parameters) (1 ex.)� Tutorial 3 : Modifying a Profile (3 ex.)� Tutorial 4 : Device Workspace Basics : Creating a Plot File (5 ex.)� Tutorial 5 : Basic Physics of the Electron Mobility in Silicon (4 ex.)� Tutorial 6 : Basic Physics of the Hole Mobility in Silicon (4 ex.)� Tutorial 7 : Carrier Mobility in MOSFETs (6 ex.)� Tutorial 8 : Carrier Mobility and Drive Current in Strained-MOSFETs (3 ex.)� Tutorial 9 : Coulomb Limited Carrier Mobility (2 ex.)� Tutorial 10 : Using the “System Layout Module” (2 ex.)

� Tutorial 10 : Using the “System Layout Module” (2 ex.)� Tutorial 11 : Using the “System Layout Module” For industrial feasibility evaluation (2 ex.)� Tutorial 12 : Inverter Delay (6 ex.)� Tutorial 13 : Device Scaling (4 ex.)� Tutorial 14 : H-K dielectric and Metal Gate Stack (3 ex.)� Tutorial 15 : Device Variability (2 ex.)� Tutorial 16 : SRAM Variability (3 ex.)� Tutorial 17 : Device Speed (1 ex.)� Tutorial 18 : III-V High Mobility Channel Materials (1 ex.)� Tutorial 19 : Device Structure – FDSOI (3 ex.)� Tutorial 20 : Device Structure – DG / FinFET (1 ex.)

Tutorial 1

General MASTAR PresentationGeneral MASTAR Presentation

Description

� Objective � this series of exercices intends to present a general

view of the MASTAR tool which will be used for all thiscourse on device physics

� Basic operation and principle are reviewed

� Pre-requisite :

� Pre-requisite :� none

Bibliography on MASTAR Model

�Introduction to MOSFET Physics, T.Skotnicki, F.Boeuf and T. Poiroux, Chapter 3 of “Physics And Operation of Silicon Devices in Integrated Circuits”, WILEY ISBN 978-1-84821-163-6

�Optimal scaling methodologies and transistor perfor mance, T. Skotnicki and F. Boeuf Chapter 6 in High-K Gate Dielectric Materials for VLSI MOSFET Applications, H. Huff and D. Gilmer, Eds. New York:Springer Verlag

T. Skotnicki & F. Boeuf6

Loading MASTAR

1. Open MASTAR directory, then double click on

MASTAR.exe

2. Read and Accept the User

Agreement

3. Click on continue

General Presentation

Device Device WorkspaceWorkspace

Roadmap Roadmap WorkspaceWorkspaceRoadmap Roadmap

WorkspaceWorkspaceAdv. Physics Adv. Physics WorkspaceWorkspace

Adv. Physics Adv. Physics WorkspaceWorkspace

What Does MASTAR Compute ?Device Device

WorkspaceWorkspaceDevice Device

WorkspaceWorkspaceRoadmap Roadmap

WorkspaceWorkspaceAdv. Physics Adv. Physics WorkspaceWorkspace

Adv. Physics Adv. Physics WorkspaceWorkspace

Input : 1 Architecture (Bulk, SOI, DG) Geometry, stress, Materials, Power supply …

Input : up to 5 architectures, year of production, familly (HP, LoP, LstP)

Input : specific to each module : Strain, Quantum confinement, FDSOI , Balistic transport…

Output : Ion, Ioff, Vth, DIBL, CET, CV/I

Graphics Output :Ion/Ioff, Vt-L, performance points (cloud), users Plot …

Graphics Output :Ion/Ioff vs CMOS node, CV/I vs Year trend-line, gate leakage vs year

Output : Basic MOSFET caracteristics

Output : (Strain) Silicon band structure (electron and holes), ballistic current, Energy level in confined inversion channel,

Usage : Device Usage : Device (reverse) engineering, (reverse) engineering, platform definition platform definition

Usage : long term view Usage : long term view of CMOS Roadmaps of CMOS Roadmaps (e.g. ITRS roadmap)(e.g. ITRS roadmap)

Usage : Fine device Usage : Fine device physics assesment. physics assesment. Longer calculation timeLonger calculation time

Device Workspace Presentation

Output Window :

Output Window : Device Performance

:Vth, Ion, Ioff, SS, DIBL, µ …

Input Window : Device Geometry, Doping, Strain… Graphical

Representation (Ion/Ioff, Vt-L, DIBL-L …

Roadmap Workspace

Input Window : up to 5 architectures

Graphical Representation of the

Output Window : Main Device output caracteristics

Representation of the Roadmaps

Tutorial 2

Creating a Profile (Saving device parameters)Creating a Profile (Saving device parameters)

Description

� Objective � this series of exercices intends to learn how to handle

the MASTAR software� Basic functions are reviewed

� Loading/saving data� Graphical representation of calculations results in real-time

� Graphical representation of calculations results in real-time

Output Window :

1. Click on View Graphics

2. Select Cloud Ion/Ioff

Ion/Ioff

Loading Default Profile

1. Click on (…) icon : this will

open the 2. Select

4. Close window

open the « load profile »

window

2. Select Default.pro

3. Click on the « Load » button

1. Device parameters are loaded from the

file Default.pro

2. Output iscalculated

3. Current Ion/Ioff point is show on the Cloud_Ion/Ioff graph

Modifing a Profile

1. Play with Nbulk arrows to change channel doping of

the MOSFET

2. Current Point is moving on Ion/Ioff

Graph3. Play with other parameters : Vdd,

Tox …

Tutorial 3

Device Workspace Basics :Device Workspace Basics :Modifying a Profile (Saving device parameters)

Description

� Creating profiles� Saving Data

� Saving Data

Output Window :

1. Click on View Graphics

2. Select Cloud Ion/Ioff

Ion/Ioff

Loading Default Profile

1. Click on (…) icon : this will

open the 2. Select

4. Close window

open the « load profile »

window

2. Select Default.pro

3. Click on the « Load » button

1. Device parameters are loaded from the

file Default.pro

2. Output iscalculated

3. Current Ion/Ioff point is show on the Cloud_Ion/Ioff graph

Ex-1 : Modifing a Profile

1. Play with Nbulk arrows to change channel doping of

the MOSFET

2. Current Point is moving on Ion/Ioff

Graph3. Play with other parameters : Vdd,

Tox …

Ex-2 : Profile Definition (1)

1. Enter Lg=39nm

2. Enter Tox=1.55nm

3. Enter Xj=15nm

4. Enter Vdd=1.1V

5. Enter Rs=180 Ohm.µm

6. Check Conventional Slope

1. Adjust Nbulk, so that Ioff=10nA/µm

1. Result is shown here

2. Click on « Save-As »

3. Name the file « ex1_LVT.pro »

4. Click on Save

Ex3 – Define another profile

1. Adjust Nbulk, so that Ioff=0.1nA/µm

2. Click on « Save As »

3. Name « ex1_SVT.pro », then

3. Name « ex1_SVT.pro », then click on Save

Tutorial 4

Device Workspace Basics :Device Workspace Basics :Creating a Plot File

Description

� Creating a plot file from existing profiles� Creating a plot file from a ASCII text file

� Creating a plot file from a ASCII text file� Adjusting the display

Generate Graphics with MASTAR

Profile (.pro)Profile (.pro)Stocks MOS Stocks MOS parametersparameters

MASTAR Plot MASTAR Plot (.plm)(.plm)

Simple Plot (.plt)Simple Plot (.plt)Ion/Ioff target Plot is Ion/Ioff target Plot is

generated from a textgenerated from a text--file file (ASCII)(ASCII)

GRAPHICS

Clouds (.clo)Clouds (.clo)

Collection of profilesCollection of profiles

Each profile is recalculated to Each profile is recalculated to generate the Ion/Ioff MASTAR generate the Ion/Ioff MASTAR

plotplot

Clouds (.clo)Clouds (.clo)Ion/Ioff is generated from a Ion/Ioff is generated from a

single profile by varying single profile by varying MOS parameters (e.g. Lg, MOS parameters (e.g. Lg,

Nbulk …)Nbulk …)

Experimental Data can be Experimental Data can be imported from a textimported from a text--filefile

Ex 1 - Creating a MASTAR Plot from previouslysaved Profiles (.pro)

1. Right-click inside the « Cloud_Ion_Ioff »

2. Select Plot > Edit/Modify Plot

Ex- 1 : Creating a Plot

1. Click on « New Plot »

1. Name the file example1.plt

Ex-1 : Creating a Plot

1. The new file appears in the plot list

Ex-1 : Creating a Plot

1. Click on « Profiles »

2. Select ex1_LVT.pro by double clicking or use

« Add>> » button. Repeat the operation with ex1_SVT.pro

3. Both selected profile should appear in the « Profile

in Plot » list

4. Click on « Apply Change », then « Close Window »

1. A « Plot » containing the

1. A « Plot » containing the previously saved profiles in

created

Ex-2 :Quick Load a Profile from a Plot

1. Put the mouse cursor on the ex1_LVT profile

2. Click on the Triangle to load the corresponding profile

into the Device Workspace

Ex – 3 : Adding another Plot (1)

1. Right-click inside the « Cloud_Ion_Ioff »

2. Select Plot > Load/Unload Plot

1. Select ITRS2003_HP_MASTAR.pl

2. Click « Add » Button

ITRS2003_HP_MASTAR.plm

3. Click « Close » Button

1. Plot is only Partially visible

2. Right click in graphic window

3. Select Modify Scale

Ex – 4 : Changing the Plot Scale

1. Set ymax=1000

2. Set xmax=2500

3. Click on Apply

Ex – 4 : Changing the Plot Scale (2)

1. ITRS Roadmap 2003 is now visible

Note :Note :

When opening a plot file (.plm), When opening a plot file (.plm), each profile (= plot component) each profile (= plot component) is recalculated. Therefore a plot is recalculated. Therefore a plot is not a simple preis not a simple pre--calculated calculated line but a realline but a real--time calculated time calculated

lineline

Ex 5 - Creating your own plot (. plt ) fromtext file

1. Open explorer and go to the MASTAR

installation directory (e.g. C:\MASTAR)

2. Go to /Data/Plots sub-directories

3. Select « plot_example.plt »

and double click

Ex – 5 : Creating your own plot (.plt) from text file

1. The file is opened in Windows Note Pad

2. Syntax is as follows

Perf. Value

[label displayed in graph]

Ion = value in µA/µm

Ioff = value in nA/µm

Displaying your plots

1. Return to MASTAR and open the

plot_example.plt file using contextual menu (righ click)

2. Graph is displayed on graph.

Note :Note :

Plot are displayed with dotted Plot are displayed with dotted line and Mastar Plot are line and Mastar Plot are

displayed with solid linesdisplayed with solid lines

Tutorial 5

Basic Physics of the Electron Mobility in Basic Physics of the Electron Mobility in Silicon

Description

� Objectives� This series of exercices intends to describe a

simplified conduction band-structure of Silicon� Conduction band is analyzed for relaxed and strained-

Silicon. From Bandstructure calculations, impact on mobility is deduced

mobility is deduced

Bibliography

� A Comprehensive Modeling Study of Two-Dimensional Si licon Subbands Using a Full-Zone k.p Method, M. Szczap, N. Cavassilas, F. Michelini, F. Payet, F. Boeuf,and T. Skotnicki, In Extented Abstracts of SSDM 2007 (JSAP CAT AP071239), pp. 462-463

� Analytical Model for Phonon-Limited Mobility in n-M OS Inversion Layers on Arbitrarily Oriented and Strained Si Surfaces, Mélanie Szczap, Nicolas Cavassilas, Frédéric Boeuf, Fabrice Payet and Thomas Skotnicki, in Extented Abstracts of SSDM 2006 (JSAP CAT AP061239), pp 1062-1063

� Strained Si/ SiGe MOSFET Capacitance modeling based on band structure

� Strained Si/ SiGe MOSFET Capacitance modeling based on band structure analysis , F. Gilibert, D. Rideau, F. Payet, F. Boeuf, E. Batail, M. Minondo, R. Bouchakour,T. Skotnicki and H. Jaouen, in Proceedings of the ESSERC 2005 (IEEE CAT 05EX1087) pp.281-285

� Low temperature characterization of effective mobil ity in uniaxially and biaxiallystrained N-MOSFETs , F. Lime, F. Andrieu, J. Derix, G. Ghibaudo, F. Boeuf and T. Skotnicki, in Proceedings of the ESSERC 2005 (IEEE CAT 05EX1087) pp.525-528

Note : I on Enhancement by materials

thGoxeDS VV

−−=2

Transistor ArchitectureMaterialProperties Velocity Velocity saturation regime

Carrier velocity under electric field E in the linear regime: v = µ E

µEcritical

Efield

Note : Mobility In Silicon

carrier, mass m*

Shockwave from lattice vibration, or impurities, or

gate oxide rugosity every τseconds 1.1. Small m* : ligth Small m* : ligth

electrons or holeselectrons or holes

2. High 2. High ττ (less possible (less possible collision)collision)

Note : Periodic Potential & Band Structure

m ∂∂=

Free ElectronElectron in aPeriodic Potential � Kröning Peyney Model

?m=m0=9.1e-31 kg

Note : Coupled States

Γ=ΨΨ 21

E1(k) E2(k)E

Two electron states are coupled � Γ

( ) 02

1 =−ΓΓ−

Eigenvalues ?

+Γ±+=

2221 δEE

Note : Bangap and Effective Masses

m ∂∂=

m<m0 or m>m0

+Γ±+=

2221 δEE

-1.E+11 -5.E+10 0.E+00 5.E+10 1.E+11

k (1/m)

m ∂∂=

Note : Silicon Band-StructureSilicon Band Structure ml

(y) 010

(z) 001

(x)100

6 equivalent types of electrons are involved in conduction regime of

2 types of holes are involved in conduction regime of pMOS : heavy and light

Note : Longitutinal and Transverse Effective Masses of Electrons

Efield

ml =0.92m0

m =0.19m

If Electric field is // to the elipsoid, then conduction mass is ml

mt=0.19m0

Efield

If Electric field is ┴ to the elipsoid, then conduction mass is mt

Note : Layout of Strain Module in MASTAR

Conduction band Iso-energy surface

Cristal and Deviceorientation configurator

StrainConfigurator

Note : Choosing Proper Cristal & Device Orientation

Select (100) substrate

Move the camera

Choose Cristal Orientation

Choose Device in-plane Orientation

Select (011) orientation

Check deviceorientation here

Ex1-Electrons : Relaxed Silicon1. Load relaxed.xps (1)2. Observe the 6-equivalent valleys of the conduction band. All Elipsoid have the same size, and relative energy shift is 0.0 eV

(2)3. Remember that electric field for transport is parallel to the « Length », i.e. along the gate length direction4. Direction along the elipsoid, (named longitudinal) have a HEAVY mass, whereas transverse direction have a lighter mass.

Note : Average conduction mass is2/3 of mt (light)

(2)2/3 of mt (light)1/3 of ml (heavy)

Ex2- Electrons : Unixial Tensile Silicon1. In the strain configurator, click on «activate » along the gate length (1)2. Default value is 1000MPa of tensile strain3. Look at the energy diagrams : Green valleys becomes bigger, meaning that their population increases. Look at the energy

shift (2)4. Lower energy valley is now deltaZ (green), in which the smaller mass is // to the electric field

• What about the mobility in tensilestrained Silicon ?

Answer :Most of the carrier will populate a lowermt mass valley. Average conduction

mt mass valley. Average conduction mass is then decreasing leading to a higher mobility

Most of carriers willpopulate the lowestenergy valley (100)

Ex3 - Electrons : Bi-axial Tensile Strained Silicon1. In the strain configurator, click on «activate » along the gate width and the gate length (1)2. Inout a value of 1500MPa of tensile strain in both direction (this is typicall of Si/SiGe20% ). Resulting stress is then bi-axial and

tensile3. Look at the energy diagrams : Green valleys becomes bigger, meaning that their population increases. Look at the energy

shift (2). Shift is higher than in the uni-axial case.4. Lower energy valley is now deltaZ (green), in which the smaller mass is // to the electric field

• What about the mobility in biaxiallytensile strained Silicon ?

Answer :Most of the carrier will populate a lowermass valley. Average conduction mass is

(2)mass valley. Average conduction mass isthen decreasing leading to a highermobility

Most of carriers willpopulate the lowestenergy valley (100)

Ex-4 : Electrons - Uniaxial Compressive Silicon1. In the strain configurator, click on «activate » along the gate gate length (1)2. Replace the value of 1500MPa of tensile strain by -1500 Mpa. This reprent a compressive uniaxial stress along the gate

length.3. Look at the energy diagrams : red and blue valleys becomes bigger, meaning that their population increases. Look at the

energy shift (2). 4. Lower energy valleys are now deltaX(red) and delta Y(blue), in which the average mass is 50%mt and 50% ml

• What about the mobility in uniaxiallystrained Silicon ?

Most of carriers willpopulate these lowestenergy valley (001) and (010)

Answer :The Z-valley has a lower enegy, so thatthere will be less light electrons. So, the average conduction mass is thenincreasing from {2/3mt,1/3ml} to {1/2mt,1/2ml} leading to a lower mobility

Tutorial 6

Basic Physics of the Hole Mobility in SiliconBasic Physics of the Hole Mobility in Silicon

Description

� Objectives� This series of exercices intends to describe a

simplified valence band-structure of Silicon� Valence band is analyzed using a 6x6 k.p. model.

Hole population and effective masses are analyzed as a function of stress

a function of stress

Ex1 : Valence Band of Silicon1. Load relaxed.xps (1)2. In theview graphic menu, select 2D band diagram, and zoom on the Valence band3. Note : the valence band is here calulated using a 6x6 k.p. Hamiltonian, giving information on the fist 3 bands. These bands

are note UP (upper), MID (middle) and LOW (lower).4. Note the effective masses computed at gamma point

Note :Most of the carriersAre in the UP and MID (degenerated)Average conduction mass along L for holes is then(0.562+0.148)/2=0.355

Ex2 : Holes - Iso Energy in the Valence Band1. In the View Graphics menu, select « 3D VB Iso Energy »2. Compute the 3D curve for the upper band, starting from 25meV from the top of the band3. A highly anisotropic structure is calculated

Note - Reading the Iso-Enegy of the Valence Band

1. The structure represent all the wave vectors of same energy. Remembering that E~k²/m*, this curve shows where k²/m* isconstant . The effective mass of holes is then highly anisotropic.

2. When m* is large (heavy holes) k² is also higher in order to keep energy constant. This is symbolized by the red « peaks » on the iso-enegy surface.

3. When m* is lower (ligh holes) k² is also lower to keep energy constant. This corresponds to the blue « divot » in the iso-energy surface

Direction with an heavy mass

Direction with an light mass

Ex3 – Holes : Uniaxial Tensile Strain1. In the strain configurator, click on «activate » along the gate length (1)2. Input a value of 1000MPa of tensile strain3. Look at the energy band diagram

• What about the hole mobility in unixaxial tensile strained Silicon ?

Answer :Most of the carrier will populate the heavier mass valley, which also becomeheavier than in relaxed silicon.Average conduction mass in thenincreasing.Mobility is decreasing

Ex4 – Holes : Uniaxial Compressive Strain1. In the strain configurator, click on «activate » along the gate length (1)2. Input a value of 2000MPa of compressive strain3. Look at the energy band diagram

• What about the hole mobility in unixaxial tensile strained Silicon ?

Answer :Most of the carrier will populate the UP valley, which also become lighter than in relaxed silicon.Average conduction mass in thendecreasing, and mobility is increasing

Note : Iso Energy of Holes with compressive uniaxial strain

Hole mass along the channel direction are now lighter than on relaxed silicon

Note : Redistribution in subbands and scattering reduction due to Strained-Si

E(LH-HH)

Si/Si0.5

BiBi--axialaxialStrainedStrained--SiSi

< 1 % in HH-0.2

Si bulk

Unstrained SiUnstrained Si

>80 % in HH

NFermi-Dirac

-0.1Ene

[100] [110]Γ

-0.3 SO

[110][100] Γ

EWhen straining Si, not only the effective mass of holes and the carrier population are changed, but also the electron-phonon interaction time is increasing leading to a better mobility

Main Stress Configurations (1)

Main Stress Configurations (2)

Summary of Stress ConfigurationsElectron Hole

Tensile - biaxial + +-Compressive - biaxial - +Tensile uniaxial - along Lg + -Compressive uniaxial- along Lg - +

uniaxialBiaxial Compression

Uniaxial Tensionalong Lg

uniaxialCompression along Lg

Biaxial Tension

Biaxial Compression

Tutorial 7

Carrier Mobility in MOSFETsCarrier Mobility in MOSFETs

Effective Mobility

� Goal of the exercise� Observe the Effective Mobility behavior as a function

of effective field� Use variation on channel doping and length� Use variation on gate oxide thickness

� Add/remove Mobility enhancement

Bibliography

� On the universality of inversion-layer mobility in n-and p-channel MOSFETs S. Takagi; M. Iwase; A. Toriumi, Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International Digital Object Identifier,10.1109/IEDM.1988.32840, Publication Year: 1988 , Page(s): 398 – 401

� On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration Takagi, S.; Toriumi, A.; Iwase, M.; Tango, H.; Electron Devices, IEEE Transactions on.Volume: 41 , Issue: 12 Digital Object Identifier: 10.1109/16.337449 Publication Year: 1994 , Page(s): 2357 - 2362

Note : Universal Mobility LawFrom S. Takagi et al.

Surface roughness limited mobility

Acoustic phonons limited mobilityµeff = f (Eeff)

µ eff)

µAC=A0Eeff1/3

µSR=A1Eeff-2

SRACeff µµµ111 +=

µ eff)

µAC=A0Eeff1/3

µSR=A1Eeff-2

SRACeff µµµ111 +=

Eeff depends on transistor parameters :

EeffEeff

Ex-1: Effective Mobility (1)1. Load Baseline.pro (nMOS transistor).2. Open Auxiliary µeff/Eff in the View Graphics menu

Ex-1: Effective Mobility (2)1. Click on the Mobility Tab2. Deactivate Strain Liner – Observe the yellow point going on the univesal curve

Ex-2: Impact of Pockets

1. Click on the Pocket tab2. Increase the Dose to 9e13 at/cm3 (1)– Observe the yellow point going on the univesal curve

• When Pocket dose ↑, the effective Mobility (µeff) decreases : why ?

Answer :When pocket dose ↑ , the Vth value isalso ↑ (2) . Since Eeff ≈ (Vg+Vth)/6Tox , Eeffis therefore ↑ , therefore µeff ↓

Ex-3 : Impact of Lgate1. Decrease gate length from 60nm down to 48nm

• Answer :When L ↓, due to short channeleffects, Vth is ↓ (1)Since Eeff ≈ (Vg+Vth)/6Tox , Eeff is also↓ , therefore µeff ↑ (2)

•Why is Effective Mobility (µeff) increasing when Lgate is ↓

Note to Pr : when decreasing L be carefull of too low Vth (<0)

Ex- 5 : Impact of Lgate at constant Ioff

1. Go back to L=60nm, then check Ioff=constant (1)2. Re-input L=48nm

Ex- 5 : Impact of Lgate at constant Ioff (2)• Effective Mobility (µeff) DECREASES with Lgate when Ioff is constant. Why ?

•Answer :1. When checking Ioff=constant,

Channel doping is adjustedautomatically to match the given Ioff

2. Due to short channel effects, the S factor is degraded from 90 to

factor is degraded from 90 to 115mV/dec when L ↓ (2)

3. To match the same Ioff, Vth has to behigher than before (307mV vs 230mV)

4. Since Eeff ≈ (Vg+Vth)/6Tox , Eeff is also↑, therefore µeff ↓ (3)

Ex-6 : Optimal Gate Length1. Uncheck Ioff=constant and go back to L=60nm2. open Auxiliary Ion(L) in the View Graphics menu (1)3. Choose Lmin=45nm, Lmax=100nm, 30 points then click on start (2)

• Saturation current of the transistor isplotted as a function of Lgate, with Ioffkept constant

kept constant• Observe the optimum of saturation current around L ≈ 60nm• for 60nm < L < 100nm, Idsat is improvedby the decreased in L• for L<60nm, the increase in Eeff isdegrading µeff more rapidly and thereforeIdsat drops.

Note to Pr : The optimum value of L depends of several technological parameters, such as Tox and Xj

Tutorial 8

Carrier Mobility and Drive Current in Strained -Carrier Mobility and Drive Current in Strained -MOSFETs

Drive Current in Strained-Si

� Goal of the exercice� Objective is to link the previous exercice on basic of mobility to the

performance of MOSFETfabricated with strained-Silicon� First, techniques to create strained-Si transistors are shown� Second,example of bi-axial strained-si devices are analysed through

MASTAR� Finally, application of local-strained-Silicon techniques is described and

simulated with MASTAR

� Pre-requisite : Basics of mobility and Mobility tutorials� Contents

� Background � Process techniques to create Strain in Silicon channel of a MOSFET transistor

Bibliography� Non-Uniform Mobility Enhancement Techniques and the ir Impact on Device Performance

Fabrice Payet, Frédéric Boeuf, Claude Ortolland* and Thomas Skotnicki, Trans. Electron Devices Volume 55, Issue 4, April 2008 Page(s):1050 – 1057

� Stress Memorization Technique (SMT) Optimization fo r 45nm CMOS , C. Ortolland, P. Morin, C. Chaton, E. Mastromatteo, C. Populaire, S. Orain, F. Leverd P. Stolk, F. Boeuf & F. Arnaud , in Digest of Tech. Papers. Symposium on VLSI Technology 2006 (IEEE CAT No 06CH37743), pp 96-97.

� Mechanical and Electrical Analysis of Strained Line r Effect in 35 nm FD SOI Devices with Ultra Thin Silicon Channels , C. Gallon, C. Fenouillet-Beranger, S. Denorme, F. Boeuf, V. Fiori, N. Loubet, A. Vandooren, T. Kormann, M. Broekaart, P. Gouraud, F. Leverd, G. Imbert, C. Chaton, C. Laviron, L. Gabette, F. Vigilant, P. Garnier, H. Bernard, A. Tarnowka, R. Pantel, F. Pionnier, S. Jullian, S. Cristoloveanu and T. Skotnicki, Jpn. J. Appl. Phys. Vol. 45 (2006) Part 1, No. 4B, pp

Jullian, S. Cristoloveanu and T. Skotnicki, Jpn. J. Appl. Phys. Vol. 45 (2006) Part 1, No. 4B, pp 3058-3063

� Strained Si/SiGe MOSFET Capacitance modeling based on band structure analysis , F. Gilibert, D. Rideau, F. Paye, F. Boeuf, E. Batail, M. Minondo, R. Bouchakour,T. Skotnicki and H. Jaouen, in Proceedings of the ESSERC 2005 (IEEE CAT 05EX1087) pp.281-285

Note : Mobility Enhancement Techniques

SubstrateSubstrate--basedbased

SixGe1-x Based

Bulk SSOI

Tensile bi -axial stress

SiGe SD

Compressive

SiGe SEG

ProcessProcess--based Induced Stessbased Induced Stess

Liners

CESL SMT

Tensile Tensile

Cristal Orientation

In-plane Out of plane

Natural mobility boost

Tensile

BULK SSOI

Tensile bi -axial stress

nMOS+pMOS

SiGe box

Compressive

Tensile

Compressive

Mod.Orientation Si Channel

Natural mobility boost

Rotated substrate

Cristal Orientation

TensileBi-axial

nMOS+pMOS

Note : Substrate-Base Strained-SiSilicon layer sees a bi-axial tensile stress when grown on relaxed Si(1-x)Ge(x)

Note : mobility improvement

Maximum mobility improvement for electrons ~ x1.8

Prepare the Exercise1. Load « baseline.pro », note the Ioff value (11.9nA/µm)2. Open the pocket tab and uncheck Pockets (1) – Ioff will increase to the lower doping

3. Adjust Nbulk to 1e18 in order to re-adjust Ioff to ~10nA/µm4. Open the mobility Tab and uncheck Activate Strain Liner

(1) (1)

Ex 1 : Global Strained by using substrate1. Open the Mobility Tab and input Kµ_sub=1.8 (i.e. max mobility improvement)2. Open the Auxiliary « Ion Strain Improvement L »Ion(L) 3. Computhe curve into a new Selection (red,blue, green or black)4. Observe how the Idsat is enhanced by the increased mobility, as a function of L

Question

• Drive current improvement is not constant with Lgate . WHY ?

Ex-1 : Answer

Long channel devices : L → ∞Vdsat → Vgt/(1+d)

Idsat ∝ µeff.vgt² ⇒ ∆Idsat/Idsat = ∆µeff/µeff

Full calculation of Id enhancement with L by F.Payet et al., T-ED

Short channel devices : L → 0Vdsat → L.Ec → L.Vsat/µeff

Idsat ∝ Vsat ⇒ ∆Idsat/Idsat = ∆ Vsat/ Vsat

Uniaxial Stress By Stressed-Liner

1.E-07

1.E-06

Strained

Unstrained

Vdd=0.9V

+15.6%

2D mecanical Simulations

Impact on nMOSFETs performancesStrained MOSFET (Lg=30nm) by

CESL Tensile

1.E-08

1.E-07

250 450 650 850Ion (µA/µm)

Tension

(F.Bœuf et al., IEDM 2004 , SSDM 2004)

Ex-2 : Local Stressor vs µeff (1)

Local stressor deposited on the top of the transistor gate createsan important stress pocket on the channel edge

Stress depends on Lgate. Mechanicalcalculation shows that :

See F.Payet et al., TED 2007

Ex-2 : Local Stressor vs µeff (2)1. Open the Mobility Tab and check Activate Local Strain2. Re-compute the Ion(L) curve into a new Selection (red,blue, green or black)3. Observe how the Idsat is enhanced by the increased mobility due to local stress

Ex-2 : Local Stressor vs µeff (3)1. Change the scale of the graphics and plot Ion(L) for L varying between 10µm and 45nm

(use the red slot)2. Uncheck « Local Strain » in the mobility tab, and use the « blue » slot to plot the Ion(L)

•Ion is more improved for short gate lengththan for long gate length. Why ?

Ex-2 : Local Stressor vs µeff (4)

• Effective Mobility (µeff) increases whenLgate decreases•This comes from the variation of the stress (deformation) applied to the transistor channel. •When L is reduced, the tensile stress pockets are overlapping, leading to and increase of mueff for shorter gate length

1. Open the view graphics tab, then select « Auxiliary Generic » (1)2. Select Lgate variation from 45nm to 10µm3. Set Lgate as X axis and Mueff as Y axis and plot the result

� with local stress , mobility is improvedon short channel transistors.(2)

Ex-3 : Local Stressor impact on Ion1. Now, open the view graphics menu and plot Auxialiry Ion Strain Improvement (L)2. Plot the graphic between 45nm and 10µm

•Ion improvement is not monotonic Why ?

Ex-3 : Local Stressor impact on Ion

Long channel devices : L → ∞Vdsat → Vgt/(1+d)

Idsat ∝ µ .vgt² ⇒ ∆I /I = ∆µ /µ

Answer :

Idsat ∝ µeff.vgt² ⇒ ∆Idsat/Idsat = ∆µeff/µeff

Short channel devices : L → 0Vdsat → L.Ec → L.Vsat/µeff

Idsat ∝ Vsat ⇒ ∆Idsat/Idsat = ∆ Vsat/ Vsat

Tutorial 9

Coulomb Limited Carrier MobilityCoulomb Limited Carrier Mobility

Description

� Objective of this tutorial is� To introduce the concept of Coulomb-Limited mobility� Analyse the impact of Coulomb Scattering (CbS) on

MOSFET performance when transistors are shrinked

� Content

� Background� Coulomb-limited Mobility Modeling� Screening Effect Modeling

� Ex-1 : plotting µeff(Eeff) curves for various channeldopings

� Ex-2: Performance evolution of scaled MOSFETs withand without CbS

Bibliography

� Modeling of carrier mobility against carrier concen tration in arsenic-, phosphorus-, and boron-doped silicon Masetti, G.; Severi, M.; Solmi, S.; Electron Devices, IEEE Transactions on . Volume: 30 , Issue: 7 Digital Object Identifier: 10.1109/T-ED.1983.21207 Publication Year: 1983 , Page(s): 764 - 769

� Impact of Coulomb Scattering on the Characteristics of NanoscaleDevices , Frédéric Boeuf, Gérard Ghibaudo* and Thomas Skotnicki, Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials, Sendai, 2009, pp1048-1049

Devices and Materials, Sendai, 2009, pp1048-1049� Accurate modeling of Coulombic scattering, and its i mpact on scaled

MOSFETs Mujtaba, A.; Takagi, S.-I.; Dutton, R.; VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on . Digital Object Identifier: 10.1109/VLSIT.1995.520876 Publication Year: 1995 , Page(s): 99 - 100

� On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration Takagi, S.; Toriumi, A.; Iwase, M.; Tango, H.; Electron Devices, IEEE Transactions on.Volume: 41 , Issue: 12 Digital Object Identifier: 10.1109/16.337449 Publication Year: 1994 , Page(s): 2357 - 2362

Note : Universal Mobility Law – Con’t

« Coulombic branch »

Coulomb Limited MobilityS

V(r)~1/r

- - - - - - - - - - - - - -- - - - - - - - - - - - - -- - - - - - - - - - - - - -- - - - - - - - - - - - - -

NeutralArea

Weak Inversion Strong Inversion

V(r)~1/r*e-k0r

Electron (holes) transport in the transistor channel is pertubated by the Coulomb potential created by fixed charges. This iscalled « Coulomb Limited Mobility »

In strong inversion, the Coulomb potentialcreated by impurities is screened by the inversion layer. This is the « Screening Effect », which lowers the impact of Coulombic interaction between carriers and impurities in the on-state of the transistor

Weak Inversion Mobility Modeling

From Massetti et al., Coulomb-limited mobility can beexpressed as a function of substrate doping concentration

(i.e. impurities concentration)

G. Masetti et al. , IEEE Trans. Elec. Dev, 1983, p764

Simple Modelisation of the Screening Effect

7.7E16 µ

2.2E18

7.7E17

7.7E16 µac

F.Bœuf et al., SSDM 2009 S. Takagi et al, T-ED, VOL. 41, NO. 12, DECEMBER 1994

Prepare the Exercise1. Load « baseline.pro », note the Ioff value (11.9nA/µm)2. Open the pocket tab and uncheck Pockets (1) – Ioff will increase to the lower doping

3. Adjust Nbulk to 1e18 in order to re-adjust Ioff to ~10nA/µm4. Open the mobility Tab and uncheck Activate Strain Liner

(1) (1)

Plotting Mobility Law : µ eff vs E eff

Vdd is used to generate Eff variation

Select Eeff for X and µeff for Y axis

Click on ComputeIn order to avoid scale issue in the displayNB : select Red then compute, then select Blue and compute, Green and compute and finally Black and compute

Ex- 1 : Plotting µ eff vs E eff

Ex-1 : Plotting µ eff vs Eeff with Coulomb Scattering[CbS] (1)

Ex- 1 : Plotting µ eff vs Eeff with Coulomb Scattering[CbS] (2)

• Change channel doping from 3e17 at/cm² to 1e18 at/cm² as shown on the graph (1)• Plot a new curve (color) for each case

Exercise 2 : CMOS L-scaling w/o CbS

L=60nmµ=281cm²/Vs, Eeff=0.94MV/cmIon=692µA/µm

Same IoffL-shrink

Coulomb interaction is off

Performance increasesthanks to reduced L-GateNB : Ioff constant must be checked !

Ex- 2 : CMOS L-scaling w/ CbS

L=50nmµ=? , Eff = ? , Ion = ?

Same IoffL-shrink

Coulomb interaction is on

Performance ? Why ?NB : Ioff constant must be checked !

Ex-2 : AnswerPerformance is this time degraded ! In order to keep Ioff constant, channel doping is increased when L isdecreased to 50nm. The CbS is then higher, and mobility is now decribes by the blue curve below which islower than the previous case (green). As a consequence, Ion is decreasing .

L=50nmIon=666µA/µm

L=60nmIon=678µA/µm

Tutorial 10

Using the “System Layout Module”Using the “System Layout Module”

Objective

� Objective is to review the basic operation of the « System Layout » module of MASTAR� Plotting I-V curves of nMOS and pMOS� Creating Layout of Inverters and SRAM� Simulating speed of Ring Oscillators

Module Overview

SRAM LayoutInverter CellMOSFET window

Id-Vd and Id-Vg

Capacitance Window

Ex- 1 : Plotting I-V curves (1)

1-Click on the green arrow to load Device profiles :nMOSpMOSPass Gate transistor for SRAM calculation

2-I-V are automatically calculated

Click in View Graphic to display graphical output window

On any graphic window, right click to open a contextual menu

e.g. on Id(Vd) curve, right click then select

Ex- 1 : Plotting I-V curves (3)

right click then select « Compute … »

Smooth = 0

adjust = 1.13Reference point from device

Smooth = 0.1

adjust = 0.93

device calculation (no interpolation)

Ex-2 : Computing Inverter Delay (1)

� To start, you need to load at least two(inverter) or 3 (SRAM) device profile (n & p + PassGate)

Cgd is automatically calculated by using Cgate+Miller (overlap+outerfringe), with gate heigth = 2*Lgate

3 – enter parasitic capacitance values

Cj,botCj,ch

4 – Input you inverter layoutIt can be saved independantly or with the whole system profile

You can enter manually the layout parameters

And save/load them

Note : Gate length comesfrom the device profile

Interter delay in then calculted automatically using a Cload= 1fFThen results for various FO are displayed

Result can be monitored by going into ViewGraphics > Tp inverter

This graph show the Vout of each inverter node in the case of a single calculation

Preference can be modified (! FanOut is not used here)

You can also generate random variation on inverter generation by checking the box, and enter the number of wanted calculation

Statiscal data on Tp @ C=1fF repartition is displayed

Ex-3 : Computing Inverter Delay includinginterconnections

Another way to compute delay is proposed by including R and C lines

IDESA CMOS Physics Using MASTAR Part 1of2x

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