HW2 Solution F15

EE477

Dr. Alice C. Parker

1c) It won’t work with only a NAND gate at the output in the feedforward path. First if we use just a NAND gate and assuming Reset_bar is available then the output Qout will be set to high. Second, this is not an alternative for a SET function because if the first latch contains data it could get moved to the second latch and be output. The solution given in 1b implements the Reset function with NAND gates. Another acceptable solution for the Reset uses NOR gates.

Charge will be shared between the top and bottom paths. Both paths are active at the same time. This causes a problem of voltage division with inputs that are 0 and 1 being read in at the same time.

Step 1) Deposit 4 layers of oxide

P-substrate

oxide

oxide

4. (5%) Sketch the steps involved in patterning metal2 using a positive photoresistance.

oxide

oxide

Step 2) Deposit the photoresist and expose with UV light through mask

P-substrate

oxide

photoresistt

mask

oxide

oxide oxide

Step 3) Develop photoresist: dissolve with a developer the soluble exposed photoresist

P-substrate

oxide

photoresistt photoresistt

oxide

oxide

Step 4) Etch and remove remaining photoresist

P-substrate

oxide

oxide

oxide oxide

oxide

oxide

Step 5) Deposit metal 2

P-substrate

oxide

oxide

oxide

Metal2

oxide

oxide

5. (5%) List the photolitography steps involved in the connection between an n+ diffusion and metal 1. Assume n+ diffusion needs to be deposited.

1) Deposit a layer of photoresist directly on the wafer 2) Expose the photoresist to light through a mask 3) Developing and removing the photoresist 4) Etching oxide 5) Exposed the wafer to donor atoms 6) Resist removal

7) Deposit 1 layer of oxide 8) Deposit photoresist 9) Expose the photoresist to light through a mask 10) Developing and removing the photoresist 11) Etching oxide 12) Deposit metal 1

NOTE: This solution ignores layers outside the contact area.

6. (5%) What are the two materials involved in the formation of the gate region?

Answer: Thin oxide and poly

7. (5%) Give one reason to use thick oxide instead of thin oxide outside of the gate region. Answer: one reason could be the prevention of parasitic transistors between adjacent diffusions.

8. (10%) Review lecture notes 4-6-F15 and 4-7-F15 and discuss in your own words the material covered by Prof. Parker, without using diagrams. Be sure to explain the materials used to make a transistor, and the changes under the gate as the gate voltage is applied.

-The substrate is p type impurities. - P – means that the impurities are distributed and we do not have a dense concentration of impurities. -The source and drain of an nmos transistors are formed with n+ impurities. -n+ means we have a dense concentration of impurities -Silicon dioxide is deposited and it acts as an insulator -Over the top in selected places we deposit polycrystalline silicon for the gate

-Accumulation: In the NMOS transistor, holes are accumulated in the channel if a voltage less than 0V is applied to the gate. There is no current flow. - Depletion region: If we apply a gate voltage greater than 0 and less than the threshold of the transistor, we attract negative charge under the gate and the holes are depleted. -We have free electrons under the gate when Vg is greater than or equal to the threshold. -We have as many free electrons as holes in accumulation. -The surface is inverted and the transistor is ON. -A channel is formed between source and drain

9. (10%) Sketch the cross section of an NMOS and a PMOS transistor and clearly label the materials and assign a number to each layer that shows the order they are deposited.

NMOS transistor:

n+ n+

D S G

p+

B

p-substrate

4 4

1

2

2 5

3

4

5

6

1 is thick oxide 2 is thin oxide 3 is poly 4 is n+ and p+ 5 is thin oxide 6 is metal 1

PMOS transistor: Assuming n-well is available

p+ p+

D S G

n+

B

n-well

1 2 5

4 4 4

2 3 5

6

1 is thick oxide 2 is thin oxide 3 is poly 4 is n+ and p+ 5 is thin oxide 6 is metal 1

10. (10%) In the figure below, draw the cross-section down into silicon along the horizontal yellow line. Contact us if you are having trouble determining layers. Green is n-well, blue is metal 1, magenta is metal 2, cyan (the lightest color) is metal 3.

P-substrate n+

p-substrate N-well

m1

m3 m3

m1

m2 m2 m2

11. (10%) In the figure below, draw the cross-section down into silicon along the vertical yellow line. Contact us if you are having trouble determining layers. Are these NMOS or PMOS transistors?

n+ n+

D S G

p-substrate

The layout has NMOS transistors.