The University of Texas at DallasDept. of Electrical Engineering

EEDG/CE 6301: Advanced Digital LogicHW # 2: Due on Tuesday June 24, 2014

When you submit your homeworks, to help us grade and identify your work, you need to comply withthe following guidelines carefully:

• Have a cover page for your homework and write clearly: (1) your name as it appears in yourstudent ID card, (2) course name/number, and (3) homework number.

• Identify the problems clearly by starting the solution of each problem on top of a new page andputting the problem number as given in the homework description. For example, for the firstproblem in this homework, you can put: HW#2 – Problem 1(a) on top of the page. Please staplethe solution pages in order as given in the homework description. If you don’t have a solution fora problem, put a blank page with the problem number on top.

1. Use the Quine-McCluskey minimization method to simplify this single-output function. Show your work.f (a,b,c,d) = ∑m(0,1,4,6,8,9,10,12)+d(5,7,14)

2. Use the Quine-McCluskey minimization method to simplify this multi-output functions. Show your work.f1(a,b,c,d) = ∑m(1,4,5,7,13)+d(3,6)f2(a,b,c,d) = ∑m(3,5,7)+d(6)f3(a,b,c,d) = ∑m(3,4,11,13,15)+d(9,14)

3. Implement the functions above using SYNOPSYS and compare the tool’s results with your hand-driven sim-plifications.

4. Consider boolean function f (a,b,c,d) = ∏M(0,3,4,11,12,13,15) ·d(2,5,6). Implement f in the followingforms:

(a) minimized form of SOP (sum of product).

(b) minimized form of POS (product of sum).

(c) minimized form of ALL-NAND.

(d) minimized form of ALL-NOR.

(e) using minimum number of 2×1 multiplexors only.

(f) using the Reed-Muller (R-M) approach to obtain the minimized EXOP (XOR of product terms) expan-sion.

(g) multi-level logic (use weak division with a divisor of your choice)

(h) multi-level logic (use strong division with a divisor of your choice)

Use SYNOPSYS to synthesize and simulate all of these circuits. In a table summarize results of synthesis interms of gate/transistor count, delay and other factors that SYNOPSYS reports or factors that you think maybe important in some applications (e.g. fan-in, fan-out).

5. ESPRESSO is a well-known two-level optimization method in which we avoid generating a list of prime im-plicants but repetitively produce expressions with fewer product terms. Three main procedures in ESPRESSOare Reduce, Expand and Irredundant. ESPRESSO can be found in many logic design books, papers and In-ternet databases. In 2 pages or less explain the general strategy and how each of the three procedures work byapplying each to a small example.

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