Hardware CompilationPie In The Sky or The Next Big Thing?

Mike Roberts

mroberts@altera.com

mbr@compsoc.net

Oxford University Computer Society - 2nd February 2000

Agenda

Semiconductors Overview Digital Design Overview Hardware Compilation Conclusions

Semiconductors Overview

In the Beginning...

Originally all digital designs implemented using individual transistors

Then using small Integrated Circuits (ICs) with 3 or 4 simple gates per chip

Still hundreds of chips required for each design!

Time Passed...

The 1980s - Application Specific Integrated Circuits (ASICs)

Either Gate Arrays or Full Custom Produced much better implementations, but

slow and expensive to develop 1990s - cell based ASICs and a compromise

of the two technologies But also...

A New Dawn!

Programmable Logic - an alternative to custom chips

Chips themselves are standard, but their behaviour is defined by the designer by selecting a configuration for the device.

Known as PLDs or FPGAs

ASICs vs. PLDs

Leading edge PLDs cannot be used for designs as large or fast as leading edge ASIC designs.

But are still adequate for many tasks! Faster time-to-market Cheaper for small to medium volumes. Possibilities of in-field reconfiguration

APEX

FLEX 10K

PLD Density Roadmap

1

10

100

1,000

10,000

Usa

ble

Gat

es (

K)

'90 '91 '92 '93 '94 '95 '96 '97 '98 '99 '00 '01 '02 '03 '04

0.25-µ,5LM

0.18-µ,7LM

0.15/0.13 µ,8LM

0.35-µ,4LM

0.10 µ,8-9LM

0.5-µ,3LM

0.8-µ,2LM

0.6-µ,2LM

1.0-µ,2LM

ClassicMAX

Beyond APEX

FLEX 8000FLEX 6000

~6 Million GatesWithin Next 5 Years

45% 43%46%

40,000Gates

400,000Gates

2 MillionGates

4 Million Gates

40%

R5000-ClassRISC Processor

MPEG-2Encoder

8-Port, 622-MHz

ATM Switch

PCI Interface

Intellectual Property in PLDs

Top 10 ASIC/PLD Suppliers: 1998

0 500 1,000 1,500 2,000

Lucent

IBM

NEC

LSI

Fujitsu

Altera

Xilinx

TI

Toshiba

VLSI

$1,645

$1,638

$1,526$1,094

$654 ($836.6 for 1999)

$629

$513

$590

$546

$1,655

Sales ($M)Ranking Includes Both Merchant Market & Intracompany Sales Source: Dataquest/Altera, preliminary April 1999

Digital Design Overview

Aims of Digital Design

To create digital hardware that is:– As fast as possible– Using as little silicon as possible– Correct– Under a set of environmental constraints

• Interfaces with rest of system

• power consumption

• etc.

Made possible using CAD (or Digitial Automation) Tools.

Design Entry

All designs used to be described using schematics of gates.

Schematics still in use today (using higher level ‘blocks’ or ‘primitives) - give a graphical way of describing the structure of a design.

Hardware Description Languages invented to allow textual equivalent of schematics.

More importantly, they can describe the behaviour of the design.

Simulation

Simulation is critical in checking the correctness of a design, especially when designing for a non-programmable technology.

Modern-day simulators can take anything from a high-level behavioural design to low-level netlist, and apply simulation vectors to allow the engineer to check the design is acting as they intended.

Synthesis

Logic Synthesis is the task of taking a behavioural design at the Logical level (commonly known as the Register Transfer Level or RTL), and producing a low-level structural view of the design (a netlist).

Synthesis Tools use various optimisation heuristics to try and produce the smallest and fastest logical structure.

This is an intractable (or class NP) problem.

Technology Mapping

Once the design has gone through logic synthesis, it must then be described in terms of the target technology.

E.g. for Altera FLEX devices, the design will use Look-up Tables for Combinatorial Logic, EABs for RAM, etc.

Again we try and optimise for most efficient use of hardware in terms of space and speed, and this is another intractable problem.

Place & Route

Finally the design must be given ‘geometry’ Each small part of the design must be placed

on the chip and must be routed in an optimal way to everything it is connected to in the design.

We can no-longer make the design any smaller, however we need to make the design as fast as possible, under the constraint that there are not infinite ‘routing resources’.

Another intractable problem!

Summary of Design Flow

Write RTL hardware design

Write fully behavioural ‘test-bench’

Simulate

Tech. Mapping

Logic Synthesis

Place & Route

Final Design

Limits of Synthesis

Synthesis Tools are the ‘state of the art’ in Digital Design, but are not perfect.

RTL still a comparatively low abstraction level. Very long design Cycle due to complexity of

design that must be given. System Design Models (e.g. Hardware /

Software Co-design systems) cannot be directly synthesised.

Hardware Compilation

What is Hardware Compilation?

Hardware Compilation is bringing software compiler concepts to the design flow of digital hardware.

The Benefits of HC

Raises the Design Entry abstraction level Shortens the Design Cycle due to lower

complexity of original design. Allows the System Model to become an

implementation in itself. Allows software engineers to design hardware!

The Challenges

What language to use?– Use HDL’s like software languages.– Use C/C++ and extend where necessary.

Is using a software language a feasible entry point for hardware design?

How do we interface with existing hardware designs?

Behavioural and Architectural Synthesis incorporate more NP problems

Language choice : using HDLs

HDLs were originally invented as simulation languages.

Their software features are limited to telling the simulator what to do.

HDLs could be extended to be provide better implementable high-level features.

Could lead to a very confused language. But hardware engineers may be able to use such

a language better than they could a software based language.

Language choice : using C

C is quite a small language, and so in theory could be used fairly simply.

Known by a very large number of hardware and software engineers.

Contains higher-level constructs than allowed in RTL HDLs

But has no concept of parallelism, communication or other hardware features.

Incorporation of extra features could get messy!

Language choice : using C++ / Java

C based Object Oriented languages are used by a large subset of C-speaking engineers.

Both have concepts of parallelism ranging from implied (distinct classes in a system) to explicit (as in Java)

Class Hierarchies could be built up expressing the features of hardware.

But both languages are huge - how do you define what is and isn’t supported?

Expressing Instruction Level Parallelism is hard.

Capturing the behavioural model

The first stages in compiling hardware would be similar to those of compiling software and would result in an Abstract Syntax Tree representing the original source code.

We then need to generate a behavioural model from this code tree. One such model is a sequencing graph, which is itself a hierarchy of data-flow graphs.

High-level Synthesis

Once we have formed a model of our design we can apply various behavioural optimisations to it, similar to those in software.

We then perform Architectural Synthesis to form an RTL description of our design.

AS is performed with knowledge of the resources available to us, and consists of 2 tasks:– Scheduling– Allocation

Difficulties

There are known algorithms for AS when you have a fixed number of specific operation resources (adders, multipliers, registers), but the task is harder for ‘generic’ hardware.

What about pipelining? How do we express the interactive nature of our

environment, such as bus protocols? For co-design tools, how do we decide what

should be implemented in hardware, and what in software?

HC Activity in Industry

ESL - HandelC http://www.embeddedsol.com/

C Level Design http://www.cleveldesign.com/

System C http://www.systemc.org/

Cynapps http://www.cynapps.com/

Frontier Design http://www.frontierd.com/

Superlog http://www.co-design.com/

Conclusions (1)

The ‘Holy Grail’ of taking any program in C and producing a hardware / software implementation that is significantly faster than it’s equivalent software-only implementation looks highly unlikely.

However, hardware compilation could work if the ‘program’ is constrained to a specific style, or a suitable new language.

But new languages are often never accepted!

Conclusions (2)

Engineering never stops where it is. A higher level entry route is required for

engineers because of the ever progressing size of hardware, and the increasing importance of ‘time-to-market’

There is now significant interest in industry in a ‘hardware-compilation’ approach.

Programmable Logic is the most suitable target for hardware compilation, and so looks set to keep on making inroads into the ASIC market.

And finally…

If Hardware Compilation becomes reality then a whole new world opens up for Programmable Logic - Reconfigurable Computing.

Tools would need to be extended, and new paradigms of programming may be required!

But that remains in the sky for now!