Post on 05-Jan-2016
description
MSP430 | Ultra-Low Power is in our DNA
Getting Started with the MSP430 LaunchPad
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
MSP430 Released Devices
Ultra-Low PowerWorld’s Lowest Power MCU• Ultra-Low Power Active Mode• 7 Low Power Modes• Instant Wakeup• All MSP430 devices are Ultra-Low Power
IntegrationIntelligent Analog & Digital Peripherals• Peripherals operate in low power modes• Minimize physical footprint and Bill of Materials• Featuring FRAM, USB, RF, Capacitive Touch I/O,
Metrology Engines, LCD, ADC, DAC & MORE
Extensive Portfolio, Low Cost Options Easy to Get StartedLow cost and simple point of entry• Complete kits starting @ $4.30• GUI-based coding & debugging tools available• MSP430Ware Software and Resource Package
-Incl. code examples, datasheets, user guides & more!
Find the right MCU for you• 400+ devices• Up 256kB Flash, 18kB RAM, 25+ package options• Devices starting at $0.25 with Value Line• Various levels of performance & integration
MSP430 MCUsAn Introduction
MSP430 | Ultra-Low Power is in our DNA
MSP430-Enabled Applications
Thousands of applications are enabled by MSP430 MCUs
Differentiation is possible with MSP430 MCU’s Ultra-Low Power performance, high analog & digital peripheral integration, and easy-to-use
tool chain.
MSP430 | Ultra-Low Power is in our DNA
Value Line: 16-bit performance, 8-bit price
1KB
2KB
4KB
8KB
14-pin TSSOP/PDIP
10 GPIO
16-pin QFN
10 GPIO
20-pin TSSOP/PDIP
16 GPIO
16KB
Flas
h Si
ze
.5 KB
32-pin QFN
24 GPIO
MSP430G2001*
MSP430G21X1*
MSP430G22X1*
ADC
Compar
ator
ADC10
SC SPI/I2 C
MSP430G21X2
UART
UART
Cap T
ouch
I/O
28-pin TSSOP
24 GPIO
MSP430G22X2
MSP430G23X2
MSP430G24X2
MSP430G21X3
MSP430G22X3
MSP430G23X3
MSP430G24X3
MSP430G25X3
SC ADC
SC ADC UART
* 8-pin SOIC in development
SC ADC
SC ADC
SC ADC
SC ADC
SC ADC
SC ADC UART
SC ADC UART
SC ADC UART
SC ADC UART
Value Line Peripherals
Value Line Peripherals General Purpose I/O
Independently programmable Any combination of input, output, and interrupt (edge
selectable) is possible Read/write access to port-control registers is supported by
all instructions Each I/O has an individually programmable pull-up/pull-
down resistor Some parts/pins are touch-sense enabled (PinOsc)
16-bit Timer_A3 3 capture/compare registers Extensive interrupt capabilities
WDT+ Watchdog Timer Also available as an interval timer
Brownout Reset Provides correct reset signal during power up and down Power consumption included in baseline current draw
Value Line Peripherals Serial Communication
USI with I2C and SPI support USCI with I2C, SPI and UART support
Comparator_A+ Inverting and non-inverting inputs Selectable RC output filter Output to Timer_A2 capture input Interrupt capability
8 Channel/10-bit 200 ksps SAR ADC 8 external channels (device dependent) Voltage and Internal temperature sensors Programmable reference Direct transfer controller send results to conversion memory
without CPU intervention Interrupt capable Some parts have a slope converter
LaunchPad Development Board
Embedded Emulation
6-pin eZ430 Connector
Part and Socket
Crystal Pads
Power Connector
Reset ButtonLEDs and Jumpers
P1.0 & P1.6
P1.3 Button
Chip Pinouts
USB EmulatorConnection
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
What is Code Composer Studio?
Integrated development environment for TI embedded processors Includes debugger, compiler, editor, simulator, OS… The IDE is built on the Eclipse open source software framework Extended by TI to support device capabilities
CCSv5 is based on “off the shelf” Eclipse (version 3.7 in CCS 5.1) Future CCS versions will use unmodified versions of Eclipse
TI contributes changes directly to the open source community Drop in Eclipse plug-ins from other vendors or take TI tools and drop them
into an existing Eclipse environment Users can take advantage of all the latest improvements in Eclipse
Integrate additional tools OS application development tools (Linux, Android…) Code analysis, source control…
Linux support soon Low cost! $445 or $495
Common Tasks Creating New Projects
Very simple to create a new project for a device using a template Build options
Many users have difficulty using the build options dialog and find it overwhelming
Updates to options are delivered via compiler releases and not dependent on CCS updates
Sharing projects Easy for users to share projects, including working with version
control (portable projects) Setting up linked resources has been simplified
ProjectSource files
Header Files
Library files
Build and tool settings
ProjectSource files
Header Files
Library files
Build and tool settings
Workspaces and Projects
WorkspaceProject 1
Project 2
Project 3
Settings and preferences
A workspace contains your settings and preferences, as well as links to your projects. Deleting projects from the workspace deletes the links, not the files
ProjectSource files
Header files
Library files
Build and tool settings
A project contains your build and tool settings, as well as links to your input files. Deleting files from the workspace deletes the links, not the files
Source filesCode and Data
Header filesDeclarations/Defines
Library filesCode and Data
LinkLink
Link
Link
Project Wizard
Single page wizard for majority of users
Next button will show up if a template requires additional settings
Debugger setup included If a specific device is selected, then
user can also choose their connection, ccxml file will be created
Simple by default Compiler version, endianness… are
under advanced settings
MSP430 | Ultra-Low Power is in our DNA
Various IDE optionsFree Integrated Development Environments (IDE) available
Code Composer Studio• Eclipse-based IDE (Compiler, debugger, linker, etc) for all TI embedded processors• Unrestricted version available for $495• Free versions are available!
• Free 16kB code-limited version available for download• Free, full-featured, 120-day trial version available
Other MSP430 IDE options are available! Learn more @ www.ti.com/msp430tools
IAR Embedded Workbench• Strong third-party IDE offering with project management tools and editor. Includes
config files for all MSP430 devices.• Free versions are available!
• Free 4/8/16kB code-limited Kickstart version available for download• Free, full-featured, 30-day trial version available
MSPGCC • Free, Open source, GCC tool chain for MSP430• includes the GNU C compiler (GCC), the assembler and linker (binutils), the debugger
(GDB)• Tools can be used on Windows, Linux, BSD and most other flavors of Unix.• Learn more @ http://mspgcc.sourceforge.net/
Lab1: Code Composer Studio
• Lab1:
• Create a new workspace
• Create Lab1 Project
• Add in temperature sense demo
• Compile it and run
18
Step 1: Create CCS workspace
• Put the Lab files onto your desktop• Launch CCS v5 Core Edition• Select a “Workspace” location
19
Step 2: Create a CCS Project• File > New > CCS Project• Project Name: Lab1• Device>Family: MSP430• Variant: MSP430G2452• Project templates and examples• : Empty Project
20
Step 3: Add a File to the CCS Project
• Project > Add Files
• Navigate to Lab source folder
• And select : Temperature_Sense_Demo.c
21
CCS Window – C/C++ Perspective OverviewIndependent Debug and C/C++ Project Perspectives1-click project Debug
Project Outline • Shortcut to project parts
Problems View • Information, Warnings, Errors
Project View• List of all Projects
Code Window • Real-time breakpoints, Syntax highlighting
Console • Build Information
22
CCS Window – Debug Perspective OverviewIndependent Debug and C/C++ Project Perspectives
1-click project Debug
Target control• Start• Stop• Halt• Stepping• Stack Trace
Code Window • Real-time breakpoints, Syntax highlighting
Program Size Info
Real-time, in-system MSP430 information• Register access• Flash, RAM, Info segment access• Disassembly view
Highly configurablewindow layout • User preferences• Plugin support
23
Step 4: Build & Debug a CCS Project
Click the “BUG” to build the
code & launch the debugger
24
Step 5: Run, Terminate a CCS Project
“TERMINATE”“RUN”
Perspectives
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
MSP430G2xx Structure
Ultra-low Power 0.1uA power down 0.8uA standby mode 220uA / 1MIPS <1us clock start-up <50nA port leakage Zero-power brown-out reset
(BOR)
Ultra-Flexible 0.5k-16kB In-System
Programmable (ISP) Flash 16-bit Timer SPI, I2C 10bit ADC Embedded emulation
FLASHClock
DigitalPeripheral
RISCCPU
16-bit
MAB 16
MDB 16
RAM
AnalogPeripheral
. . .
. . .
ACLK
SMCLK
JT
AG
/De
bu
g
6
015
16
16-bit ALU
R8
R9
R10
R11
R12
R13
R14
R15
R4
R5
R6
R7
R3/CG
R2/SR
R1/SP
R0/PC
16
015
16
16-bit ALU
R8
R9
R10
R11
R12
R13
R14
R15
R4
R5
R6
R7
R3/CG
R2/SR
R1/SP
R0/PC
16
16-bit RISC CPU
Deep single-cycle register file 4 special purpose 12 general purpose No accumulator
bottleneck RISC architecture
27 core instructions 24 emulated instructions 7 address modes
Atomic memory-to-memory addressing
Bit, byte and word processing
Constant generator
7
Memory Map
Interrupt Vector Table
Flash/ROM
InformationMemory
RAM
16-bitPeripherals
8-bitPeripherals
8-bit Special FunctionRegisters
Flash programmable via JTAG or In-System (ISP)
ISP down to 2.2V. Single-byte or Word
Main memory: 512 byte segments (0-n). Erasable individually or all
Information memory: 64 byte segments (A-D) Section A contains device-specific
calibration data and is lockable Programmable Flash Memory
Timing Generator
0Fh
0h
0FFh010h
01FFh0100h
02FFh0200h
FFDFh0E00h
0FFFFh0FFE0h
G2452 shown
010FFh01000h
MCLKCPU
SMCLKPeripherals
ACLKPeripherals
16MHzDCO
Min. Puls Filter
VLO
OSC_Fault
Clock System Very Low Power/Low Frequency
Oscillator (VLO) 4 – 20kHz (typical 12kHz) 500nA standby 0.5%/°C and 4%/Volt drift
Crystal oscillator (LFXT1) Programmable capacitors Failsafe OSC_Fault Minimum pulse filter
Digitally Controlled Oscillator (DCO) 0-to-16MHz + 3% tolerance Factory calibration in Flash
On PUC, MCLK and SMCLK are sourced from DCOCLK at ~1.1 MHz. ACLK is sourced from LFXT1CLK in LF mode with an internal load capacitance of 6pF.
G2xxx - No Crystal Required DCO
// Setting the DCO to 1MHz if (CALBC1_1MHZ ==0xFF || CALDCO_1MHZ == 0xFF)
while(1); // Erased calibration data? Trap!
BCSCTL1 = CALBC1_1MHZ; // Set range
DCOCTL = CALDCO_1MHZ; // Set DCO step + modulation G2xx1 devices have 1MHz DCO constants only. Higher frequencies must be manually calibrated G2xx2 & G2xx3 have all 4 constants + calibration values for the ADC & temperature sensor
Run Time Calibration of the VLO
Calibrate the VLO during runtime Clock Timer_A runs on calibrated 1MHz DCO Capture with rising edge of ACLK/8 from VLO fVLO = 8MHz/Counts Code library on the web (SLAA340)
TAR
Calibrated 1 MHz DCO
CCRx
ACLK/8 from VLO
fVLO = 8MHz/Counts
System MCLK & Vcc
Match needed clock speed with required Vcc to achieve the lowest power
External LDO regulator required Unreliable execution results if Vcc < the minimum required for the selected frequency All G2xxx device operate up to 16MHz
Lab2: Basic Clock Configure
• Lab2
• Import Lab2 project to Workspace
• Setup DCO = 1MHz
• Use DCO/8 as MCLK, LED Blink
• Use VLO/8 as MCLK, LED Blink
Lab 2:
// Configure Basic ClockBCSCTL1 = __________; // Set rangeDCOCTL = ___________;// Set DCO step + modulationBCSCTL3 |= LFXT1S_2;// Set LFXT1
// Configure Basic ClockBCSCTL1 = __________; // Set rangeDCOCTL = ___________;// Set DCO step + modulationBCSCTL3 |= LFXT1S_2;// Set LFXT1
• Reference User’s Guide, Datasheet & Schematic
// Configure MCLKBCSCTL2 |= ________ + DIVM_3; // Set MCLK
// Configure MCLKBCSCTL2 |= ________ + DIVM_3; // Set MCLK
Lab 2: BCSCTL2 in 2xx User Guide
Lab 2: BCSCTL2 in MSP430G2453 head file
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
Interrupts and the StackEntering Interrupts
Any currently executing instruction is completed The PC, which points to the next instruction, is pushed onto the stack The SR is pushed onto the stack The interrupt with the highest priority is selected The interrupt request flag resets automatically on single-source flags;
Multiple source flags remain set for servicing by software The SR is cleared; This terminates any low-power mode; Because the
GIE bit is cleared, further interrupts are disabled The content of the interrupt vector is loaded into the PC; the program
continues with the interrupt service routine at that address
Vector TableInterrupt Source Interrupt
FlagSystem
InterruptWord Address Priority
Power-upExternal Reset
Watchdog Timer+Flash key violation
PC out-of-range
PORIFGRSTIFGWDTIFG
KEYVReset 0FFFEh 31
(highest)
NMIOscillator Fault
Flash memory access violation
NMIIFGOFIFG
ACCVIFG
Non-maskableNon-maskableNon-maskable
0FFFCh 30
0FFFAh 29
0FFF8h 28
Comparator_A+ CAIFG maskable 0FFF6h 27
Watchdog Timer+ WDTIFG maskable 0FFF4h 26
Timer_A3 TACCR0 CCIFG maskable 0FFF2h 25
Timer_A3 TACCR1 CCIFG TAIFG
maskable 0FFF0h 24
0FFEEh 23
0FFECh 22
ADC10 ADC10IFG maskable 0FFEAh 21
USI USIIFG USISTTIFG
maskable 0FFE8h 20
I/O Port P2 (2) P2IFG.6
P2IFG.7
maskable 0FFE6h 19
I/O Port P1 (8) P1IFG.0 toP1IFG.7
maskable 0FFE4h 18
0FFE2h 17
0FFE0h 16
Unused 0FFDEh to 0FFCDh 15 - 0
ISR Coding
#pragma vector=WDT_VECTOR
__interrupt void WDT_ISR(void)
{
IE1 &= ~WDTIE; // disable interrupt
IFG1 &= ~WDTIFG; // clear interrupt flag
WDTCTL = WDTPW + WDTHOLD; // put WDT back in hold state
BUTTON_IE |= BUTTON; // Debouncing complete
}
#pragma vector - the following function is an ISR for the listed vector
_interrupt void - identifies ISR name
No special return required
Controlling GPIO Ports
P1DIR |= BIT4; P1SEL |= BIT4;
P1DIR |= BIT4; P1SEL |= BIT4;
P1DIR |= BIT0; P1OUT |= BIT0;
P1DIR |= BIT0; P1OUT |= BIT0;
26
Input Register PxIN
Output Register PxOUT
Direction Register PxDIR
Function Select PxSEL
Interrupt Edge PxIES
Interrupt Enable PxIE
Interrupt Flags PxIFG
For GPIO Int
Function Select PxREN
Function Select PxSEL2
GPIO RegisterGPIO Register GPIO Code ExampleGPIO Code Example
Pin Muxing
Each pin has multiple functionsRegister bits select pin functionSee device specific datasheet
Lab3: GPIO
Lab3• Setup P1.3 to Button• Setup P1.0 to LED control• LED toggle with Button
Lab 3:
P1DIR |= BIT0; // Set P1.0 to output directionP1IES |= BIT3; // P1.3 Hi/lo edge_____ &= ~BIT3; // P1.3 IFG cleared_____ |= BIT3; // P1.3 interrupt
P1DIR |= BIT0; // Set P1.0 to output directionP1IES |= BIT3; // P1.3 Hi/lo edge_____ &= ~BIT3; // P1.3 IFG cleared_____ |= BIT3; // P1.3 interrupt
// Port1 interrupt service routine#pragma vector = ____________interrupt void Port_1(void)
// Port1 interrupt service routine#pragma vector = ____________interrupt void Port_1(void)
// Port1 interrupt service routineP1OUT ^= BIT0; // P1.0 = toggle______ &= ~BIT3; // P1.3 IFG cleared
// Port1 interrupt service routineP1OUT ^= BIT0; // P1.0 = toggle______ &= ~BIT3; // P1.3 IFG cleared
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
Timer_A
Asynchronous16-Bit timer/counter
Continuous,up-down,up count modes
Multiple capture/compare registers
PWM outputs Interrupt vector
register for fastdecoding
Can trigger DMA transfer
On all MSP430s
Compararator 2
CCI
CountMode
SetTAIFG
TACCR2
ACLKSMCLK
TACLK
INCLK
GNDVCC
CCI2ACCI2B
SetCCIFG2
OutputUnit2
CCR0
SCCI Y AEN
CCR1
CCR2
CaptureMode
16-bit TimerTAR
70
Timer_A Counting Modes
0FFFFh
0h
CCR0
Stop/Halt Timer is halted
UpTimer counts between 0 and CCR0
0FFFFh
0h
Continuous Timer continuously counts up
0FFFFh
0h
CCR0
UP/DOWN Mode
Up/Down Timer counts between 0 and CCR0 and 0
CCR – Count Compare Register
71
Timer_A Interrupts
TACCR1 CCIFG
TACCR2 CCIFG
TAIFG
TIMERA1_VECTORTAIV
TACCR1, 2 and TA interrupt flags are prioritized and combined using the Timer_A Interrupt Vector Register (TAIV) into anotherinterrupt vector
TACCR0 CCIFG TIMERA0_VECTOR
The Timer_A Capture/Comparison Register 0 Interrupt Flag (TACCR0) generates a single interrupt vector:
Your code must contain a handler to determine which Timer_A1 interrupt triggered
No handler required
72
TAIV Handler Example
#pragma vector = TIMERA1_VECTOR__interrupt void TIMERA1_ISR(void){ switch(__even_in_range(TAIV,10)) { case 2 : // TACCR1 CCIFG P1OUT ^= 0x04; break; case 4 : // TACCR2 CCIFG P1OUT ^= 0x02; break; case 10 : // TAIFG P1OUT ^= 0x01; break; }}
#pragma vector = TIMERA1_VECTOR__interrupt void TIMERA1_ISR(void){ switch(__even_in_range(TAIV,10)) { case 2 : // TACCR1 CCIFG P1OUT ^= 0x04; break; case 4 : // TACCR2 CCIFG P1OUT ^= 0x02; break; case 10 : // TAIFG P1OUT ^= 0x01; break; }}
0xF814 add.w &TAIV,PC0xF818 reti 0xF81A jmp 0xF8240xF81C jmp 0xF82A0xF81E reti0xF820 reti 0xF822 jmp 0xF8300xF824 xor.b #0x4,&P1OUT0xF828 reti0xF82A xor.b #0x2,&P1OUT0xF82E reti0xF830 xor.b #0x1,&P1OUT0xF834 reti
0xF814 add.w &TAIV,PC0xF818 reti 0xF81A jmp 0xF8240xF81C jmp 0xF82A0xF81E reti0xF820 reti 0xF822 jmp 0xF8300xF824 xor.b #0x4,&P1OUT0xF828 reti0xF82A xor.b #0x2,&P1OUT0xF82E reti0xF830 xor.b #0x1,&P1OUT0xF834 reti
IAR C code Assembly code
Source TAIV ContentsNo interrupt pending 0TACCR1 CCIFG 02hTACCR2 CCIFG 04hReserved 06hReserved 08hTAIFG 0AhReserved 0ChReserved 0Eh
0
TAIV
15
xxxx00000000000
0
73
Completely automatic Independent frequencies with different duty cycles can be generated
for each CCR Code examples on the MSP430 website
Timer_A PWM Example
TEST
Vcc
P2.5Vss
XOUT
XIN
RST
P2.0
P2.1
P2.2
TA2/P1.7
P1.6
P1.5
P1.4
P1.3
TA1/P1.2
P1.1
P1.0
P2.4
P2.3
MSP430F11x1
CCR0
CCR1
CCR0
CCR1
CCR0
CCR1
CCR2 CCR2 CCR2
74
Direct Hardware Control With Timer_A
TACCR1:Ref delay / ADC trigger
TAIFG: Reference & ADC on
TAR
0
TACCR1 = 557
65536
ADC12IFG: Process ADC result Ref/ADC Off
CPU Active Mode
17ms
2s
Example: ADC12
UART ...75
WDT+ Module: Overview
• Found on all MSP430 devices
• Two modes Watchdog Interval timer
• Access password protected
• Separate interrupt vectors for POR and interval timer
• Sourced by ACLK or SMCLK
• Controls RST/NMI pin mode
• WDT+ adds failsafe/protected clock
16-BitCounter
PasswordCompare
EQU
EQUR / W
MDBWDTCTL
ControlRegister
Watchdog Timer Failsafe Operation
If ACLK / SMCLK fail, clock source = MCLK(WDT+ fail safe feature)
If MCLK is sourced from a crystal, and the crystal fails, MCLK = DCO(XTAL fail safe feature)
Fail-Safe Logic
16-bitCounter
A EN
SMCLK
ACLK
MCLK
1
1
CLK
WDTSSEL WDTHOLD
WDT clock source …
WDT: Common Design Issues
• Program keeps resetting itself!
• Program acting wacky – how did execution get to that place? Try setting interrupt near beginning of main() to see if code is re-starting
• CPU seems to freeze before even getting to first instruction Is this a C program with a lot of initialized memory? Generally can occur only with very large-memory versions of the device Solution: Use __low_level_init() function, stop watchdog there
void main(void) { WDTCTL = WDTPW+WDTHOLD; // Stop the dog . .}
void main(void) { WDTCTL = WDTPW+WDTHOLD; // Stop the dog . .}
WDT: Interval Timer Function
• No PUC issued when interval is reached
• If WDTIE and GIE set when interval is reached, a WDT interval interrupt generated instead of reset interrupt
• Selectable intervals
Lab4: Timer and Interrupts
Lab4
• Use TimerA to implement Lab2
• Configure Timer_A3 Count Cycle: 5100
•Occurs a interrupt when TAR =100
Lab 4:
// Configure TimerATACTL = __________________; // Source: ACLK, UP modeCCR0 = 5100; //Timer count 5100CCR1 = 100; //Timer count 100CCTL0 = CCIE; //CCR0 interrupt enabledCCTL1 = CCIE; //CCR1 interrupt enabled
// Configure TimerATACTL = __________________; // Source: ACLK, UP modeCCR0 = 5100; //Timer count 5100CCR1 = 100; //Timer count 100CCTL0 = CCIE; //CCR0 interrupt enabledCCTL1 = CCIE; //CCR1 interrupt enabled
// Timer A0 interrupt service routine#pragma vector = ____________interrupt void Timer_A0(void)
// Timer A0 interrupt service routine#pragma vector = ____________interrupt void Timer_A0(void)
// Timer A1 interrupt service routine#pragma vector = ____________interrupt void Timer_A1(void)
// Timer A1 interrupt service routine#pragma vector = ____________interrupt void Timer_A1(void)
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
Ultra Low Power Feature
MSP430 designed for ULP from ground up
Peripherals optimized to reduce power and minimize CPU usage
Intelligent, low power peripherals can operate independently of CPU and let the system stay in a lower power mode longerwww.ti.com/ulp
Ultra-Low Power Is In Our DNA
Multiple operating modes100 nA power down (RAM retained)0.3 µA standby110 µA / MIPS from RAM 220 µA / MIPS from Flash
Instant-on stable high-speed clock
1.8 - 3.6V single-supply operation
Zero-power, always-on BOR
<50nA pin leakage
CPU that minimizes cycles per task
Low-power intelligent peripheralsADC that automatically transfers
dataTimers that consume negligible
power100 nA analog comparators
Performance over required operating conditions
Ultra-Low Power Activity Profile
Minimize active timeMaximize time in Low Power Modes Interrupt driven performance on-demand with <1μs wakeup timeAlways-On, Zero-Power Brownout Reset (BOR)
Active
Low Power Mode
Average
OffAll
Clocks Off100nA
Stand-byDCO offACLK on
0.3µA
LPM3• RTC function• LCD driver• RAM/SFR retained
CPU Off DCO on
ACLK on45µA
MSP430 Low Power Modes
LPM0 LPM4• RAM/SFR retained
ActiveDCO on
ACLK on220µA
<1µs
<1µs
Specific values vary by device
BOR is
enabled in
all modes
Low Power Mode Configuration
Active Mode 0 0 0 0 ~ 250uA
LPM0 0 0 0 1 ~ 35uA
LPM3 1 1 0 1 ~ 0.8uA
LPM4 1 1 1 1 ~ 0.1uA
bis.w #CPUOFF,SR ; LPM0 bis.w #CPUOFF,SR ; LPM0
R2/SR
Reserved CSCG1 SCG0 ZNGIECPUOFF
OSCOFFV
LPM in Assembly34
ORG 0F000h RESET mov.w #300h,SP mov.w #WDT_MDLY_32,&WDTCTL bis.b #WDTIE,&IE1 bis.b #01h,&P1DIR
Mainloop bis.w #CPUOFF+GIE,SR xor.b #01h,&P1OUT jmp Mainloop
WDT_ISR bic.w #CPUOFF,0(SP) reti
ORG 0FFFEh DW RESET ORG 0FFF4h DW WDT_ISR
ORG 0F000h RESET mov.w #300h,SP mov.w #WDT_MDLY_32,&WDTCTL bis.b #WDTIE,&IE1 bis.b #01h,&P1DIR
Mainloop bis.w #CPUOFF+GIE,SR xor.b #01h,&P1OUT jmp Mainloop
WDT_ISR bic.w #CPUOFF,0(SP) reti
ORG 0FFFEh DW RESET ORG 0FFF4h DW WDT_ISR
Item1
Item2
PC
SR=0018
SP
SP
Item1
Item2
PC
SR
Item1
Item2
PC
SR=0008
SPItem1
Item2
Low Power Modes In Stack
LPM in C35
ULP is Easy!
Using our Low Power Modes are easy
void main(void){ WDT_init(); // initialize Watchdog Timer while(1) { __bis_SR_register(LPM3_bits + GIE); // Enter LPM3, enable interrupts activeMode(); // in active mode. Do stuff! }}
#pragma vector=WDT_VECTOR__interrupt void watchdog_timer (void){ __bic_SR_register_on_exit(LPM3_bits); // Clear LPM3 bits from 0(SR), Leave LPM3, enter active mode}
void main(void){ WDT_init(); // initialize Watchdog Timer while(1) { __bis_SR_register(LPM3_bits + GIE); // Enter LPM3, enable interrupts activeMode(); // in active mode. Do stuff! }}
#pragma vector=WDT_VECTOR__interrupt void watchdog_timer (void){ __bic_SR_register_on_exit(LPM3_bits); // Clear LPM3 bits from 0(SR), Leave LPM3, enter active mode}
= LPM3 + RTC_Function
0.80µA + 250µA * 100µs
1000000µs
0.80µA + 0.030µA = 0.83µA
Time
1mA
1µA
100µA
10µA
// Partial RTC_Function incrementseconds(); incrementminutes(); incrementhours();//
// Partial RTC_Function incrementseconds(); incrementminutes(); incrementhours();//
32768
Interface
MSP430F20x1
10-yr Embedded Real-Time Clock
Low-Power Operation Power-efficient MSP430 apps:
Minimize instantaneous current draw Maximize time spent in low power modes
The MSP430 is inherently low-power, but your design has a big impact on power efficiency
Proper low-power design techniques make the difference
“Instant on” clock
100% CPU Load
Move Software Functions to Peripherals
MCUP1.2
// Endless Loop for (;;) { P1OUT |= 0x04; // Set delay1(); P1OUT &= ~0x04; // Reset delay2();}
// Endless Loop for (;;) { P1OUT |= 0x04; // Set delay1(); P1OUT &= ~0x04; // Reset delay2();}
// Setup output unit CCTL1 = OUTMOD0_1; _BIS_SR(CPUOFF);
// Setup output unit CCTL1 = OUTMOD0_1; _BIS_SR(CPUOFF);
Zero CPU Load
47
Power Manage Internal Peripherals
P1OUT |= 0x02; // Power dividerCACTL1 = CARSEL + CAREF_2 + CAON; // Comp_A onif (CAOUT & CACTL2) P1OUT |= 0x01; // Faultelse P1OUT &= ~0x01; P1OUT &= ~0x02; // de-power divider CACTL1 = 0; // Disable Comp_A
P1OUT |= 0x02; // Power dividerCACTL1 = CARSEL + CAREF_2 + CAON; // Comp_A onif (CAOUT & CACTL2) P1OUT |= 0x01; // Faultelse P1OUT &= ~0x01; P1OUT &= ~0x02; // de-power divider CACTL1 = 0; // Disable Comp_A
Comparator_A
Px.x
Ref
+
-
CAON
MSP430F20x1
P1.0
48
Op-amp with shutdown can be 20x lower total power
MCUMCU
Sensor
TLV2760
SD
ADC
Px.xSensor
"1uA OPA"
ADC
0.01uA = Shutdown
20uA = Active
---------------------------
0.06uA = Average
1uA = Quiescent
1uA = Active
-----------------------
1uA = Average
Power Manage External Devices
49
Unused Pin Termination Digital input pins subject to shoot-through current
Input voltages between VIL and VIH cause shoot-through if input is allowed to “float” (left unconnected)
Port I/Os should Driven as outputs Be driven to Vcc or ground by an external device Have a pull-up/down resistor
Lab5: Low Power Mode
Lab5
• Optimize Lab4 to implement LPM
Lab 5:
_BIS_SR(_________);//Enter Low Power Mode;_BIS_SR(_________);//Enter Low Power Mode;
Enter Low Power Modes with just 1 line of code!
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
Fast Flexible ADC10
10-bit 8 channel SAR ADC 6 external channels Vcc and internal temperature
200 ksps+ Selectable conversion clock Autoscan
Single Sequence Repeat-single Repeat-sequence
Internal or External reference Timer-A triggers Interrupt capable Data Transfer Controller (DTC) Auto power-down
RAM, Flash, Peripherals
S/H 10-bit SAR
ADC10SCTA1
TA2TA0
Direct Transfer
Controller
VR- VR+
AVCCAVSS
1.5V or 2.5V
Auto
Batt Temp
DirectTransfer
Controller
DataTransfer
Controller
Sample Timing
Reference must settle for <30uS Selectable hold time 13 clock conversion process Selectable clock source
- ADC10OSC (~5MHz)
- ACLK
- MCLK
- SMCLK
70 Cycles / Sample
Fully Automatic
Autoscan + DTC Performance Boost
Data2Data1Data0Data2
ADC
DTCAU
TO
// Autoscan + DTC _BIS_SR(CPUOFF);// Autoscan + DTC _BIS_SR(CPUOFF);
// Software Res[pRes++] = ADC10MEM;ADC10CTL0 &= ~ENC; if (pRes < NR_CONV) { CurrINCH++; if (CurrINCH == 3) CurrINCH = 0; ADC10CTL1 &= ~INCH_3; ADC10CTL1 |= CurrINCH; ADC10CTL0 |= ENC+ADC10SC;}
// Software Res[pRes++] = ADC10MEM;ADC10CTL0 &= ~ENC; if (pRes < NR_CONV) { CurrINCH++; if (CurrINCH == 3) CurrINCH = 0; ADC10CTL1 &= ~INCH_3; ADC10CTL1 |= CurrINCH; ADC10CTL0 |= ENC+ADC10SC;}
Comparator_A
References usable internally and externally
Low-pass filter selectable by software
Input terminal multiplexer
One interrupt vector with enable
CAOUT
+
-
VCC
CAEX
0.5xVCC
0.25xVCC
set CAIFGFlag
CA0
CA1
CCI1B+
-
0V
GDS
VCC0V
CAON
CAREF
0.25xVCC
+-
~0.55V
REFPx.x
Px.x
VSS
Timer_ACapture
Comparator-Based Slope ADC
10-bit+ accuracy Resistive sensors Very low cost App note SLAA038
R_NTC = 10k xt_NTCt_10k
t_x = R_x x C x lnVccCAREFV
. . .
R_NTC
10k
t_NTCV
VccR_NTC = 10k x
t_NTC
t_10k
CAREF
=
C x ln
t_10kV
VccCAREFC x ln
Example: Thermistor
RREF = 10K, RM = NTC VCAREF = VCC*e(-t/RC) Relationship simplifies to single
multiply & divide operations
Timer Triggers – Low-Power
// Interrupt CPU cycles; MSP430 ISR to start conversion 6 BIS #ADC12SC,&ADC12CTL0 ; Start conversion 5 RETI ; Return 5 ; 16
// Interrupt CPU cycles; MSP430 ISR to start conversion 6 BIS #ADC12SC,&ADC12CTL0 ; Start conversion 5 RETI ; Return 5 ; 16
Memory
ADC
Timer
Timer triggered interrupts – no software wait loops
64
Selecting an MSP430 ADC
Voltage range to be measured? Max frequency for AIN? How much resolution? Differential inputs? Reference range? Multiple channels?
min max Ref IN Ref OUT Ref I_OUT
ADC10 8 34 200+ 10 57 Vss to Vref 1.4-3.6 1.5/2.5V +/-1mA SW/Timer/Cont N/A DTCADC12 12 34 200+ 12 68 Vss to Vref 1.4-3.6 1.5/2.5V +/-1mA SW/Timer/Cont N/A Conv Mem
SD16 3 ind 16 85 +/-600mV 1.0-1.5 1.2V +/-1mA SW/Cont to 32x PreloadSD16_A 4 mux'd ~0.03 ~5 16 85 +/-600mV 1.0-1.5 1.2V +/-1mA SW/Cont to 32x Buffered input
triggering gain features
~4
f SAM PLE (ksps) referencechannels res
SINAD (typ)
A IN
Slope
Bits
10 100 1k 10k 100k 1M
SAR
Sigma-Delta
Samples per Second
8
12
16
20
24
Lab6: ADC10
• Measure internal temperature
•Additional CCS features
Lab 6:
//Configure ADC10// Choose ADC Channel as Temp SensorADC10CTL1 = _______ + ADC10DIV_3; //Choose ADC Ref sourceCCTL1ADC10CTL0 = _______ + ADC10SHT_3 + REFON + ADC10ON +ADC10IE;
//Configure ADC10// Choose ADC Channel as Temp SensorADC10CTL1 = _______ + ADC10DIV_3; //Choose ADC Ref sourceCCTL1ADC10CTL0 = _______ + ADC10SHT_3 + REFON + ADC10ON +ADC10IE;
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
USI
MSP430G2xx1/2 devices Variable length shift
register Supports I2C
START/STOP detection SCL held after START SCL held after counter
overflow Arbitration lost
detection Supports SPI
8/16-bit Shift Register MSB/LSB first
Flexible Clocking Interrupt Driven
8/16-Bit Shift Register
SDASDI
SCLSCLK
USIIFG
USIIFG
USISTTIFG
SMCLK
SCLKACLK
TA1TA2
SWCLKTA0
DividerHOLD
USIIFG
SCL Hold
Bit CounterSTARTSTOPDetect
SDO
USISTTIFGUSISTP
83
USI for Data I/O
Data shift register: up to 16 bits supported
Number of bits transmitted and received is controlled by a bit counter
Transmit and Receive is simultaneous
Data I/O is user-defined: MSB or LSB first
Bit counter automatically stops clocking after last bit & sets flag
No data buffering needed
USISSELx
USIIFG
Bit Counter
Data I/O
Set USIIFG
USICNTx
SMCLKSMCLK
SCLKACLK
TA1TA2
USISWCLKTA0
Clock Divider/1/2/4/8…/128
USIDIVx
HOLD
Data ShiftRegister
84
//Shift16_inout_SoftwareSR = DATA;for (CNT=0x10;CNT>0;CNT--){ P2OUT &= ~SDO; if (SR & 0x8000) P2OUT |= SDO; SR = SR << 1; if (P2IN & SDIN) SR |= 0x01; P2OUT |= SCLK; P2OUT &= ~SCLK; }
//Shift16_inout_SoftwareSR = DATA;for (CNT=0x10;CNT>0;CNT--){ P2OUT &= ~SDO; if (SR & 0x8000) P2OUT |= SDO; SR = SR << 1; if (P2IN & SDIN) SR |= 0x01; P2OUT |= SCLK; P2OUT &= ~SCLK; }
USI Reduces CPU Load for SPI
425 Cycles
10 Cycles
// Shift16_inout_USI USISR |= DATA;USICNT |= 0x10;
// Shift16_inout_USI USISR |= DATA;USICNT |= 0x10;
Peripheral
SDO
SCLK
SDIN
MSP430
I2C Slave has as little as 4us from clock edge to data
Traditional software-only solution allows time for little else
USI hardware enables practical and compliant I2C
Code on MSP430 website
85
USCI Designed for Ultra-Low Power:
Auto-Start from any Low-Power Mode
Two Individual Blocks: USCI_A:
UART or SPI USCI_B:
SPI or I2C Double Buffered TX/RX Baudrate/Bit Clock Generator:
Auto-Baud Rate Detect Flexible Clock Source
RX glitch suppression DMA enabled Error Detection
SMCLK Baud Rate Generator
Serial Interface
ACLK
SPIUART
IrDAUCx
Bit Clock Generator
Serial Interface
ACLKSMCLK
I2CSPI
UCBxCLK
UCAxCLK
USCI_B
USCI_A
7
UCx4
Recommended USCI initialization/re-configuration process is shown in your workbook.
88
USCI Enhanced Features New standard MSP430 serial interface Auto clock start from any LPMx Two independent communication blocks Asynchronous communication modes
UART standard and multiprocessor protocols UART with automatic Baud rate detection
(LIN support) Two modulators support n/16 bit timing IrDA bit shaping encoder and decoder
Synchronous communication modes SPI (Master & Slave modes, 3 & 4 wire) I2C (Master & Slave modes)
UxRXBUF
URXD
SMCLK
UCLKIACLK
SMCLK
Receiver Shift Register
Baud-Rate Generator
Transmit Shift Register
UxTXBUF
Clock Phase and Polarity UCLK
UTXD
SOMI
SIMO
STE
89
USCI Baudrate Generator
Prescaler/Divider
UCAxBR0
1st Modulator BITCLK16
UCAxBR1
88
UCBRSx3
UC0CLKACLK
SMCLKSMCLK
LSB
/16
2nd Modulator BITCLK
UCBRFx4
BITCLK16
1 Bit
Sampling for majority votes
RXD
Oversampling Baud Rate Generation Two Modulators:
UCBRSx and UCBRFx select modulation pattern RX sampled using BITCLK16
90
Value Line Communication Modules
Universal SerialCommunication Interface
G2xx1/2
Universal SerialInterface
G2xx3
Two modulators; supports n/16 timings- Auto baud rate detection- IrDA encoder & decoder- Simultaneous USCI_A . and USCI_B (2 channels)
- - -
Two SPI (one each on USCI_A and USCI_B)- Master and slave modes- 3 and 4 wire modes
- One SPI available
- Master and slave modes
- Simplified interrupt usage- Master and slave modes - Up to 400kbps
- SW state machine needed- Master and slave modes
USCI USI
SPI
I2C
UART
82
Low-Overhead UART Implementation
100% hardware bit latching and output Full speed from LPM3 and LPM4 Low CPU Overhead App Note SLAA078 on web
P2.2/TA0 TA0/P1.1MSP430
Start - CCR0 = TAR- add 1.5 bit length to CCR0- switch to compare mode
compare - logic level latched in SCCI - add 1 bit length to CCR0
Stop
OUTMODx
OutputUnit0
SCCI Y AEN Capture/Compare
TXD
RXD
76
Software UART Implementation
A simple UART implementation, using the Capture & Compare features of the Timer to emulate the UART communication
Half-duplex and relatively low baud rate (9600 baud recommended limit), but 2400 baud in our code (1 MHz DCO and no crystal)
Bit-time (how many clock ticks one baud is) is calculated based on the timer clock & the baud rate
One CCR register is set up to TX in Timer Compare mode, toggling based on whether the corresponding bit is 0 or 1
The other CCR register is set up to RX in Timer Capture mode, similar principle
The functions are set up to TX or RX a single byte (8-bit) appended by the start bit & stop bit
Application note: http://focus.ti.com/lit/an/slaa078a/slaa078a.pdf
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
GraceTM
Grace™
A free, graphical user interface that generates source code and eliminates
manual peripheral configuration
Visually Enable & Configure MSP430 Peripherals
Developers can interface with buttons, drop downs, and text fields to effortlessly navigate high above low-level register settings
Grace generates fully commented C code for all F2xx and G2xx Value Line Microcontrollers from MSP430
01/26/2011 TI Confidential – NDA Restrictions 98
What is Grace?
Grace – Graphical Code Engine
Is:• Generates MSP430 peripheral initialization code in CCSv4• Enable a new user to have running program in 15 minutes• Heavy emphasis on ease of use• Currently in “Public Beta” stage• Will extend to cover all MCU devices
Is not:• Graphical application builder
01/26/2011 TI Confidential – NDA Restrictions 99
Project Structure and Build Flow
ApplicationC/C++
Source Files
“xxxxx.cfg”This is the device peripheral configuration file and
is edited with the graphical Grace view.
“src” FolderAutomatically generated inside the “Debug” or
“Release” folder. Contains MSP430 C-code that initializes all configured peripherals.
C/C++ Compiler Linker Final ExecutableMSP430 Output File
01/26/2011 TI Confidential – NDA Restrictions 100
User Code Skeleton Example/*
* ======== Standard MSP430 includes ========
*/
#include <msp430.h>
/*
* ======== Grace related includes ========
*/
#include <ti/mcu/msp430/csl/CSL.h>
/*
* ======== main ========
*/
int main(int argc, char *argv[])
{
// Activate Grace-generated configuration
CSL_init();
__enable_interrupt(); // Set GIE
// >>>>> Fill-in user code here <<<<<
return (0);
}
Performs all Grace-configured peripheral setup
User code from here…
You know this one…
Master include file for all Grace-related content
01/26/2011 TI Confidential – NDA Restrictions 101
Grace – Adding a Peripheral
• Right-click on the peripheral and select “Use”• All blocks shaded blue can be configured
01/26/2011 TI Confidential – NDA Restrictions 102
How to tell a peripheral is added?
• Look at the bottom left corner of the peripheral on the CSL view, it will show a checkmark if the peripheral is initialized.
01/26/2011 TI Confidential – NDA Restrictions 103
Grace – Navigation
• Left-click on a peripheral to navigate to its detail view• Use home button to go back to the top-level device view• Forward/backward buttons are available as well
01/26/2011 TI Confidential – NDA Restrictions 104
Grace – Configuring a Peripheral
• Each peripheral has 4 different representations:“Overview,”“Basic User”,“Power User”,“Registers”
• You can edit anyof the them, theyare all connected
• Validate thecurrent config byclicking “Refresh”
01/26/2011 TI Confidential – NDA Restrictions 105
Grace – Removing a Peripheral
• Right-click on the peripheral and select “Stop Using”
Lab8: Grace
• Use Grace to configure all the required peripherals
• To do Lab3 again
• Enter LPM4
01/26/2011 TI Confidential – NDA Restrictions 107
Lab 8: step by step
• Disable the Watchdog timer• Configure the DCO to run off the internal pre-calibrated
8MHz constants• Setup the LaunchPad’s S2 button for interrupt operation• Enter LPM4 in the main() function• Provide a button interrupt handler that clears the IFGs and
wakes up the MCU upon return• Toggle between the red LED in main()• Enter LPM4 in the main() again
Agenda
• Introduction to Value Line
• Code Composer Studio
• CPUX and Basic Clock Module
• Interrupt and GPIO
• TimerA and WDT+
• Low-Power Optimization
• ADC10 and Comparator_A+
• Serial Communications
• Grace
• Capacitive Touch Solution
What is Capacitive Touch?
text
C1 C2
C3 C4
A change in Capacitance …
When a conductive element is present - Finger or stylus• Add C3 and C4, resulting in an increase in capacitance C1 + C2 + C3||C4• This becomes part of the free space coupling path to earth ground
When the dielectric (typically air) is displaced• Thick gloves or liquid results in air displacement and change in dielectric• Capacitance is directly proportional to dielectric, capacitance (C2) increases (air ~1, everything else > 1)
MSP430 Capacitive Touch Options
Pin oscillator method (PinOsc with internal RO)No external components requiredTimer usedCurrently MSP430G2xx2 and MSP430G2xx3
1uA/Button
10uA/Button
< 3uA/Button
RO method Most robust against interference
Timer used, comparator used
MSP430 devices with comparator
RC method Lowest power method
Supports up to 16 keys
GPIO plus timer used
Any MSP430 device
Library Structure
Butt
onBu
tton
Slid
erSl
ider
Prox
imity
Prox
imity
Capa
cita
nce
Sens
orCa
paci
tanc
e Se
nsor
APPLICATION LAYER:APPLICATION LAYER:
CompensationCompensation
PHYSICAL LAYER:PHYSICAL LAYER:
Filter Method Type:Filter Method Type:
RCRC
RORO
Fast
Sca
n RO
Fast
Sca
n RO
Whe
elW
heel
0/1 Z X A
PinO
scPi
nOsc
16bit
Capacitance
CAP
TOU
CH
LAYE
RCA
P TO
UCH
LA
YER
Determination of threshold crossingDetermination of threshold crossing
Sens
or D
elta
Sens
or D
elta
Offset
Array of deltas
SCHEDULERSCHEDULER
HALHAL
Element: Port I/O
definitions
Sensor:ElectrodesReferenceSensor TypeMeasurement MethodPeripheralsPeripheral settingsMeasurement Parameters
Schedule:SensorPeripheralsPeriod definition
Configuration
Capacitive Touch BoosterPack
• Capacitive Touch plug-in for LaunchPad
• Touch button, scroll wheel & proximity sensor
• Includes MSP430G2xx2 with Cap Touch I/O module
• Example design for scroll wheels & Proximity sensor
• Full support for Capacitive Touch Library
• Only $10• www.ti.com/capacitivetouch
Part Number: 430BOOST-SENSE1
Thank you!