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Gábor C. Temes

School of Electrical Engineering and Computer Science

Oregon State University

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Switched-Capacitor Circuit Techniques

ORIGIN :

•  "SC" replacing "R"; 1873, James Clerk Maxwell, "A TREATISE ON ELECTRICITY AND MAGNETISM", PP. 420-421.

•  IC Context: 1972, D. L. Fried. Low-, high- and bandpass (n-path!) SC filters.

•  Application as ADCs: 1975, Mccreary and Gray.

•  1977, UC Berkeley, BNR, AMI, U. of Toronto, Bell labs., UCLA, etc.: Design of high-quality SC filters and other analog blocks. Liou, Brglez, Tsividis et al.: CAD tools for SC.

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Switched-Capacitor Circuit Techniques BASIC PRINCIPLE: •  Signal entered and read out as voltages, but processed internally as

charges on capacitors. Since CMOS reserves charges well, high SNR and linearity are possible.

IMPORTANCE: •  Replaces absolute accuracy of R & C (10-30%) with matching

accuracy of C (0.05-0.2%); •  Can realize accurately and tunably large RC time constants; •  Can realize high-order circuits with high dynamic range; •  Allows medium-accuracy data conversion without trimming; •  Can realize large mixed-mode systems for telephony, audio,

aerospace, physics etc. applications on a single CMOS chip. •  Tilted the MOS VS. BJT contest decisively.

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Switched-Capacitor Circuit Techniques COMPETING TECHNIQUES:

•  Switched-current circuitry: Can be simpler and faster, but achieves lower dynamic range & much more THD. Needs more power. Can use basic digital technology; now SC can too!

•  Continuous-time filters: much faster, less linear, less accurate, lower dynamic range.

FUTURE:

•  Continues to be bright in low & medium-speed applications: low-power, low-voltage, digital CMOS operation possible.

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LCR Filters to Active-RC Filters

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Typical Applications of SC Technology –(1)

Line-Powered Systems:

•  Telecom systems (telephone, radio, video, audio) •  Digital/analog interfaces •  Smart sensors •  Instrumentation •  Neural nets. •  Music synthesizers

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Typical Applications of SC Technology –(2)

Battery-Powered Micro-Power Systems:

•  Watches •  Calculators •  Hearing aids •  Pagers •  Implantable medical devices •  Portable instruments, sensors •  Nuclear, biomedical, environmental array sensors (micro-power,

may be battery powered).

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New SC Circuit Techniques To improve accuracy: •  Oversampling, noise shaping •  Dynamic matching •  Digital correction •  Self-calibration •  Offset/gain compensation

To improve speed, selectivity: •  GaAs technology •  BiCMOS technology •  N-path, multirate circuits

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Typical SC Stages

•  Amplifiers: programmable, precision, AGC, buffer, driver, sense amplifiers

•  Filters •  S/H and T/H stages •  MUX and deMUX stages •  PLLs •  VCOs •  Modulators, demodulators •  Precision comparators •  Attenuators •  ADC/DAC blocks

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Active - RC Integrator

Can be transformed by replacing R1 by an SC branch.

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SC Integrator (Analog Accumulator) Stray insensitive version:

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SC Integrator (Analog Accumulator)

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Low-Q Tow-Thomas SC Biquad – (1)

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Low-Q SC Biquad – (2)

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Low-Q SC Biquad – (3)

Approximate design equations for ω0T << 1:

>1,

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Low-Q SC Biquad – (4)

For b0 = 1, matching coefficients:

Preliminary Ci values. Scaling to follow!

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High-Q Biquad – (1)

Figure 5.11. (a) High Q switched-capacitor biquad; (b) clock and signal waveform

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High-Q Biquad – (2)

Approximate design equations :

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High-Q Biquad – (3) Exact equations:

For b2 = 1, matching gives C spread & sensitivities reasonable even for high Q & fc/fo, since C2, C3, C4 enter only in products

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Linear Section – (1)

Original φi : pole/zero btw 0 & 1.

Parenthesized: zero > 1.

For differential circuit no restrictions.

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Linear Section – (2) To achieve negative zero or pole, at . Cst effect is usually small.

Nonlinearity!

Stray insensitive branch (cannot be used as feedback branch!).

Figure 5.12. Switched-capacitor linear section: (a) complete circuit; (b) and (c) alternative input branches.

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Cascade Design – (1)

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Cascade Design – (2)

Easy to design, layout, test, debug, Passband sensitivities “moderate” ; 0.1 - 0.3 dB/% in passband. Stopband sensitivites good. Pairing of num. & denom., ordering of sections affect S/N, element spread and sensitivities. Rules of thumb or search for optimum. (Put high-Q pole in middle, aim for flat gain in each stage.) (See Sedra & Brackett book.)

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Cascade Design – (3) Choose Cascade Order

The next decision is to order the biquads (and maybe a first-order term) in the situation to best meet chip specifications.

Many practical factors influence the optimum ordering. A few examples (John Khouri, personal communication): 1. Order the cascade to equalize signal swing as much as possible for dynamic range considerations 2. Choose the first biquad to be a lowpass or bandpass to reject high frequency noise, to prevent overload in the remaining stages. 3. lf the offset at the filter output is critical, the last stage should be a highpass or bandpass to reject the DC of previous stages

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Cascade Design – (4)

4. The last stage should NOT in general be high Q because these stages tend to have higher fundamental noise and worse sensitivity to power supply noise 5. In general do not place allpass stages at the end of the cascade because these have wideband noise. It is usually best to place allpass stages towards the beginning of the filter. 6. If several highpass or bandpass stages are available one can place them at the beginning, middle and end of the filter. This will prevent input offset from overloading the filter, will prevent internal offsets of the filter itself from accumulating (and hence decreasing available signal swing) and will provide a filter output with low offset. 7. The effect of thermal noise at the filter output varies with ordering; therefore, by reordering several dB of SNR can often be gained. (John Khouri, unpublished notes)

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Ladder Filter For optimum passband matching, for nominal ∂Vo/∂x ~ 0 since Vo is maximum x values. x: any L or C.

Use doubly-terminated LCR filter prototype, with 0 flat passband loss. State equations:

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The Exact Design of SC Ladder Filters

Purpose: Ha(sa) ↔ H(z), where

Then, gain response is only frequency warped.

State equations for V1,I1 &V3; Example:

Purpose of splitting C1:

has a simple z-domain realization.

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Sa-domain block diagram

Realization of input branch: Qin=Vin/saRs, which becomes,

This relation can be rewritten in the form

or, in the time domain

Δqin(tn) : incremental charge flow during tn-1 < t < tn, in SCF

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Alternative realization a. Simple, but stray sensitive:

b. Stray insensitive:

Hence, it remains a capacitor C′2 in the z domain.

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Central block implementation –(1)

Hence, it contributes a charge

To the adders at the input terminals of the first and third integrators. Replacing sa with (2/T)[(z-1)/(z+1)], we get

The z-transform of the incremental charge Δq(tn), ΔQ(z), is thus

which can be rewritten in the form

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Central block implementation –(2)

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Damping resistors in input & output stages –(1)

The input branch can be used here, but it is easier to take

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Damping resistors in input & output stages –(2)

Using bandpass realization tables to obtain low-pass response gives an extra op-amp, which can be eliminated:

Sixth-order bandpass filter: LCR prototype and SC realization.

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To find voltage swings, compute histograms or frequency responses. To modify Vo → kVo ; Yi/Yf → kYi/Yf ∀i. Hence, change Yf to Yf /k or Yi to kYi. (It doesn't matter which; area scaling makes the results the same.) To keep all output currents unchanged, also Ya → Ya/k, etc.

Noise gain :

Scaling for Optimal DR and Chip Area –(1)

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Hence, . The output noise currents are also divided

by k, due to Y′a = Ya/k, etc. Hence, the overall output noise from this stage changes by a factor

where : the signal gain.

Scaling for Optimal DR and Chip Area –(2)

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The output signal does not change, so the SNR improves with increasing k. However, the noise reduction is slower than 1/k, and also this noise is only one of the terms in the output noise power.

If Vo> VDD, distortion occurs, hence k ≤ kmax is limited such that Yo saturates for the same Vin as the overall Vout. Any k > kmax forces the input signal to be reduced by k so the SNR will now decrease with k.

Scaling for Optimal DR and Chip Area –(3)

Conclusion: kmax is optimum.

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Purposes :

1. Maximum dynamic range 2. Minimum Cmax / Cmin , ∑C / Cmin 3. Minimum sens. to op-amp dc gain

effects.

Scaling of SCF's. –(1)

1. Dynamic range Opamps have eq. input noise v2

n, max. linear range |Vmax|. For optimum dynamic range Vin max / Vin min, each opamp should have the same Vimax(f), so they all saturate at the same Vin max. Otherwise, the S/N of the op-amp is not optimal.

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To achieve V1 max = V2 max = ••• = Vout max, amplitude scaling:

Scaling of SCF's. –(2)

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Multiply h(z)& g1,2,3 by ki; then Yi becomes Yi/ki, but ΔQ′1,2,3 will not change. Choose ki= Vi max/ Vout max. Since g & h are proportional to the Cj in the branch, multiply all Cj connected or switched to the output of opamp i by ki!

Scaling of SCF's. –(3)

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Scaling of SCF's. –(4) 2. Minimum Cmax/Cmin If all fn(z) & h(z) are multiplied by the same li:

will not change. Choose li = Cmin / Ci min where Ci min is the smallest C connected to the input of op-amp i, and Cmin is the smallest value of cap. permitted by the technology (usually 0.1 pF ≤ Cmin ≤ 0.5 pF for stray-insensitive circuits). Big effect on Cmax / Cmin!

3. Sensitivities The sens. of the gain to Ck remain unchanged by scaling; the sens. to op-amp gain effects are very much affected. Optimum dynamic-range scaling nearly optimal for dc gain sens. as well.

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Scaling of SCF's. –(5)

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Scaling of SCF's. –(6) G

AIN

/ dB

FREQUENCY / Hz

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Scaling of SCF's. –(7) G

AIN

/ dB

FREQUENCY / Hz

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Scaling of SCF's. –(8) G

AIN

/ dB

FREQUENCY / Hz

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SC Filters in Mixed-Mode System Two situations; example:

Situation 1: Only the sampled values of the output waveform matter; the output spectrum may be limited by the DSP, and hence VRMS,n reduced. Find VRMS from charges; adjust for DSP effects.

Situation 2: The complete output waveform affects the SNR, including the S/H and direct noise components. Usually the S/H dominates. Reduced by the reconstruction filter.

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Direct-Charge-Transfer Stage –(1)

Advantages: Opamp does not participate in charge transfer → no slewing distortion, clean S/H output waveform. Finite DC gain Ao introduces only a scale factor K = 1/[1+1/Ao]. Feedback factor = 1.

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Direct-Charge-Transfer Stage –(2) Analysis gives

where

is the ideal lowpass filter response.

Applications:

• SC-to-CT buffer in smoothing filter for D-S DAC (Sooch et al., AES Conv., Oct. 1991) • DAC + FIR filter + IIR filter (Fujimori et al., JSSC, Aug. 2000).

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Double Sampled Data Converter –(1)

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Double Sampled Data Converter –(2)

-DAC

+DAC

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Double Sampled Data Converter –(3)

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Double Sampled Data Converter –(4)

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Double Sampled Data Converter –(5)

DAC

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Double Sampled Data Converter –(6)

• Mismatch in C1 & C2 affects only CM charge, which is effectively rejected by differential structure. • No extra factor enters the loop transfer function • Modulator stability and coefficients are preserved.

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Double Sampled Data Converter –(7)

2nd order, OSR=64, 3-bit quantizer and 0.1% DAC mismatch (MATLAB simulation)

[1] K. Lee et al., EL 2007

[2] D. Senderowicz et al.,

JSSC 1997

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Parallel Pipeline A/D Converter