Post on 21-Feb-2018
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General ideaConfiguration technologies
Organization of hardware resourcesCommercial aspects
Extensions of the basic ideaThe FPL design flow
Field-Programmable Logic
Prof. Hubert KaeslinMicroelectronics Design Center
ETH Zurich
Morgan Kaufmann Top-Down Digital VLSI Design Chapter 2
last update: July 18, 2014
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General ideaConfiguration technologies
Organization of hardware resourcesCommercial aspects
Extensions of the basic ideaThe FPL design flow
Content
You will learn
how field-programmable logic works and what variations are available.
I Functioning and organization of field-programmable logic (FPL)I Configuration technologies(one-time vs. many-times programmable)I FPGAs vs. CPLDs architectures
I Commercial aspectsI Overview on FPL device families
I The price of electrical configurabilityI Extensions of the basic idea
I Design flow for FPL devices
I The benefits and limitations of FPL e
e
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General ideaConfiguration technologies
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Extensions of the basic ideaThe FPL design flow
Introduction
I The term programmable is a misnomer as there is no program,no instruction sequence to execute.
I As opposed to mask-programmed ICs,field-programmable logic (FPL)uses neither custom layout structures, nor proprietary photomasks,nor bespoke wafer processing steps to create the circuit to be.
I Instead, pre-manufactured subcircuits get configuredinto the targetcircuitvia purely electrical means.
Sounds too good to be true. Think of how this might be achieved!
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G
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General ideaConfiguration technologies
Organization of hardware resourcesCommercial aspects
Extensions of the basic ideaThe FPL design flow
General idea I: Hardware resources before configuration
(reprinted with permission from D. Strukov, K. Likharev: Reconfig. Nano-Crossbar
Architectures in Nanoelectronics and Information Technology, Wiley-VCH, 2012)c Hubert Kaeslin Microelectronics Design Center ETH Zurich Field-Programmable Logic 4 / 4 6
G l id
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Extensions of the basic ideaThe FPL design flow
General idea II: Target functionality
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General idea
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General ideaConfiguration technologies
Organization of hardware resourcesCommercial aspects
Extensions of the basic ideaThe FPL design flow
General idea III: Circuit after configuration
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General idea
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General ideaConfiguration technologies
Organization of hardware resourcesCommercial aspects
Extensions of the basic ideaThe FPL design flow
First understanding
Observation
Field-programmable devices are best understood as soft hardware.
As opposed to this, firmware must be viewed as hard software.
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Organization of hardware resourcesCommercial aspects
Extensions of the basic ideaThe FPL design flow
A closer look
Key properties of any FPL device depend on choices along two dimensions.
Organization of hardware resourcesWhat are the prefabricated hardware resources made available
to customers? 1How can they be made to form a larger circuit?
Configuration technologyWhat are the programmable links?
How is the configuration stored?How many times can it be changed?Can this be done without removing the device from the board?
1Customers = designers who want to implement their own circuits in an FPL device.c Hubert Kaeslin Microelectronics Design Center ETH Zurich Field-Programmable Logic 8 / 4 6
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General ideaConfiguration technologies
Organization of hardware resourcesCommercial aspects
Extensions of the basic ideaThe FPL design flow
Static memoryFlash memoryAntifuses
Subject
Configuration technologies
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General idea
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Configuration technologiesOrganization of hardware resources
Commercial aspectsExtensions of the basic idea
The FPL design flow
Static memoryFlash memoryAntifuses
Configuration technologies for field-programmable logic
have their roots in memories: SRAM 7 a)Flash memory 7 b)PROM 7 Fuse c) andAntifuse d)
a)
static memory cell
electronicswitch
c)
layout view
(to be blown or notnarrow constriction
during programming)
d)
cross section
base material
thin dielectric layer(to be ruptured or notduring programming)
metal
metal
b)
control gate(used for programming only)
floating gate(acting as charge trap)
cross section
metal metal
source drain
Figure: Electrical connections that can be doneand undoneby electrical means.c Hubert Kaeslin Microelectronics Design Center ETH Zurich Field-Programmable Logic 10/46
General idea
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Configuration technologiesOrganization of hardware resources
Commercial aspectsExtensions of the basic idea
The FPL design flow
Static memoryFlash memoryAntifuses
a) SRAM-based FPL devices
I Configuration data stored in static memory cells steer MOSFET switches.
Pros and cons:
+ Unlimited in-circuit reprogrammability
Huge overhead in terms of transistor count and area
Volatile(configuration gets lost whenever circuit is powered down)
The need to (re-)obtain the configuration from outside at power-up
is solved in one of three possible ways: by reading from a dedicated off-chip ROM(bit-serial or bit-parallel),
by downloading a bit stream from a host computer, or
by long-term battery backup.
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General ideaC fi
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Configuration technologiesOrganization of hardware resources
Commercial aspectsExtensions of the basic idea
The FPL design flow
Static memoryFlash memoryAntifuses
Operation principles of flash memory I
I A floating gate is sandwiched between bulk material and a control gate.
I The electrical charge trapped there governs MOSFET conductivity.
metal metal
source drain
ee
Programming
Hot electroninjection
+
+
a)
Programming occurs by way ofhot electron injectionfrom the channel.A stronglateral fieldaccelerates electrons to the point wherethey get injected through the thin dielectric layer into thefloating gate. The necessary programming voltage on the orderof 5 to 20 V is generated by an on-chip charge pump.
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General ideaC fi ti t h l i
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Configuration technologiesOrganization of hardware resources
Commercial aspectsExtensions of the basic idea
The FPL design flow
Static memoryFlash memoryAntifuses
Operation principles of flash memory II
I A floating gate is sandwiched between bulk material and a control gate.
I The electrical charge trapped there governs MOSFET conductivity.
metal metal
source drain
e e
Erasure
Fowler-Nordheimtunneling
! !
b)
Erasure removes trapped electrons by having them tunnel through theoxide layer underneath by way ofFowler-Nordheim tunnelingthat occurs when a strongvertical field( 8 ... 10 MV/cm)is applied across the gate oxide.
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General ideaConfiguration technologies
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Configuration technologiesOrganization of hardware resources
Commercial aspectsExtensions of the basic idea
The FPL design flow
Static memoryFlash memoryAntifuses
b) Flash-based FPL devices
I Electrical charges trapped on floating gates turn MOSFET switchespermanently on or off.
Pros and cons:
+ Non-volatile(no need to be configured following power-up)
+ Reconfigurable through package pins (no need for UV exposure)
+ Data retention times 10 to 40 years
Endurance 100 to 1000 configure-erase cycles (less than for flash memory)
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General ideaConfiguration technologies
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Configuration technologiesOrganization of hardware resources
Commercial aspectsExtensions of the basic idea
The FPL design flow
Static memoryFlash memoryAntifuses
d) Antifuse-based FPL devices
I Thin dielectrics are selectively ruptured to establish conductive paths.
Pros and cons:
Programming is permanent+ No need to be configured following power-up New part required for each bug fix or design update
+ Higher layout densities than with reprogrammable links(antifuses are only about the size of a contact or via)
+ Less sensitive to radiation
+ Superior protection against unauthorized cloning
1Fuse-based programming was a historical episode in FPL technology.c Hubert Kaeslin Microelectronics Design Center ETH Zurich Field-Programmable Logic 15/46
General ideaConfiguration technologies
S i
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Configuration technologiesOrganization of hardware resources
Commercial aspectsExtensions of the basic idea
The FPL design flow
Static memoryFlash memoryAntifuses
FPL configuration technologies compared
Non Live at Reconfi- Unlimit. Area ExtraConfiguration vola- power gurable endu- occupation fabr.technology tile up rance per link steps
SRAM no no in circuit yes large 0Flash memory yes yes in circuit no small > 5Antifuse PROM yes yes no n.a. smallest 3
Ideal yes yes in circuit yes zero 0
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Configuration technologiesOrganization of hardware resources
Commercial aspectsExtensions of the basic idea
The FPL design flow
Simple programmable logic devices (SPLD)Field-programmable gate arrays (FPGA)
Subject
Organization of hardware resources
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General ideaConfiguration technologies
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g gOrganization of hardware resources
Commercial aspectsExtensions of the basic idea
The FPL design flow
Simple programmable logic devices (SPLD)Field-programmable gate arrays (FPGA)
Complex programmable logic devices (CPLD)I Overall organization has evolved from purely combinational devices.
equivalent to
one SPLD
programmableinterconnect
CPLDc)
ANDplane
ORplane
PLA
inputs outputs
a)
logicprogrammable
ANDplane
ORplane
SPLD
flip-flops & feedback
inputs outputs
b)
programmablefeedback
logicprogrammable
evolutiontechnological
evolutiontechnological
flip-flops
&
feedback
AND
plane
OR
plane
configurableI/O cell
Figure: General architecture of CPLDs (c) along with precursors (a,b).c Hubert Kaeslin Microelectronics Design Center ETH Zurich Field-Programmable Logic 18/46
General ideaConfiguration technologies
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Organization of hardware resourcesCommercial aspects
Extensions of the basic ideaThe FPL design flow
Simple programmable logic devices (SPLD)Field-programmable gate arrays (FPGA)
Field-programmable gate arrays (FPGA)
I Overall organization patterned after mask-programmed gate-arrays.
logiccell
config.
switchbox
conf.
configurableI/O cell
wires
FPGA
wires
Figure: General architecture of FPGAs.c Hubert Kaeslin Microelectronics Design Center ETH Zurich Field-Programmable Logic 19/46
General ideaConfiguration technologies
O i i f h d Si l bl l i d i (SPLD)
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Organization of hardware resourcesCommercial aspects
Extensions of the basic ideaThe FPL design flow
Simple programmable logic devices (SPLD)Field-programmable gate arrays (FPGA)
Fine-grained FPGAs
I A few logic gates and/or one bistable per configurable logic cell.
Actel logic tile
INP1
as clock
INP2may serve
OUP1to local routing
OUP2to long routing
may serveINP3
as reset
a)
subcircuitscontrolled by
configuration bits
Figure: Example: logic tile from Actel ProASIC.
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General ideaConfiguration technologies
O i ti f h d Si l bl l i d i (SPLD)
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Organization of hardware resourcesCommercial aspects
Extensions of the basic ideaThe FPL design flow
Simple programmable logic devices (SPLD)Field-programmable gate arrays (FPGA)
Coarse-grained FPGAs
I Combinationalfunctions of
four or morevariables.I Two or more
bits stored perconfigurablelogic cell.
b)
Xilinx slice
LUTconfig.
D Q
ENA
SR
REV
CLK
or
XQ
X
XMUX
XB
F5
YQ
Y
YMUX
YB
FX
D Q
CLK
G1
G2
G3
G4
F1
F2
F3
F4
SR
CE
BY
BX
FXINAFXINB
CIN
LUTconfig.
ENA
SR
REV
CLK
or
Figure: Example: logic slice from Xilinx Virtex-4 (2 4-input LUTs, 2 bistables).c Hubert Kaeslin Microelectronics Design Center ETH Zurich Field-Programmable Logic 21/46
General ideaConfiguration technologies
Organization of hardware resources Simple programmable logic devices (SPLD)
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Organization of hardware resourcesCommercial aspects
Extensions of the basic ideaThe FPL design flow
Simple programmable logic devices (SPLD)Field-programmable gate arrays (FPGA)
There has been a trend towards even coarser granularities
Figure: LUT granularity trade-offs at the 65 nm technology node.
I The optimum trade-offfor LUTs has shifted from 4 to 6 inputsover the last couple of generations.
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General ideaConfiguration technologies
Organization of hardware resources Simple programmable logic devices (SPLD)
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Organization of hardware resourcesCommercial aspects
Extensions of the basic ideaThe FPL design flow
Simple programmable logic devices (SPLD)Field-programmable gate arrays (FPGA)
Coarse-
grainedFPGAs
2nd example:logic slice(slicel)from XilinxVirtex-6
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General ideaConfiguration technologies
Organization of hardware resources Simple programmable logic devices (SPLD)
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Organization of hardware resourcesCommercial aspects
Extensions of the basic ideaThe FPL design flow
Simple programmable logic devices (SPLD)Field-programmable gate arrays (FPGA)
Coarse-
grainedFPGAs
3rd example:adaptive logicmodule(ALM)from AlteraStratix V
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General ideaConfiguration technologies
Organization of hardware resources An overview on FPL device families
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O g uCommercial aspects
Extensions of the basic ideaThe FPL design flow
The price and the benefits of electrical configurability
Subject
Commercial aspects
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General ideaConfiguration technologies
Organization of hardware resources An overview on FPL device families
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gCommercial aspects
Extensions of the basic ideaThe FPL design flow
The price and the benefits of electrical configurability
An overview on FPL device families
Overall organization of hardware resourcesConfiguration CPLD FPGAtechnology coarse grained fine grained
Static Xilinx Virtex, Kintex, Atmel AT6000,memory Artix, Spartan. AT40K.(SRAM) Lattice SC, EC, ECP.
Altera Stratix,Arria, Cyclone.eASIC Nextreme SL.Achronix Speedster.
Flash Xilinx XC9500, Lattice XP Actel ProASIC3,memory CoolRunner-II. MACH XO. ProASIC3 nano,
Altera MAX. Igloo,
Lattice MACH 1,...,5. Fusion.Cypress Delta39K,
Ultra37000,PSoC 1,...,5LP.
Antifuse QuickLogic Eclipse II, Actel MX,(PROM) PolarPro. Axcelerator AX.
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General ideaConfiguration technologies
Organization of hardware resources An overview on FPL device families
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Commercial aspectsExtensions of the basic idea
The FPL design flow
The price and the benefits of electrical configurability
The benefits of electrical configurability
+ Agility. Being able to (re)define a parts functionality after fabrication
is extremely valuable in the marketplace.+ Simpler design flow.Many issuesthat must be addressed in extenso
when designing a custom IC are implicitly solved in an FPL device.
+ Applications that mandated a custom ASIC a few years agofit into a single FPL device today, and this trend is to carry on.
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General ideaConfiguration technologiesOrganization of hardware resources
C i lAn overview on FPL device familiesTh i d h b fi f l i l fi bili
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Commercial aspectsExtensions of the basic idea
The FPL design flow
The price and the benefits of electrical configurability
The price of electrical configurability I
To provide for configurability, FPL must accommodate extraI transistors, programmable links,I interconnect lines, vias,I lithographic masks, and wafer processing steps.
The required and the prefabricated hardware resources never quite match,
leaving part of the manufactured gates unused. Field-programmable logic is unlikely to rival hardwired logic
on the grounds of integration density, unit costsandenergy efficiency.
From comparisons of SRAM-based FPGAs against cell-based ASICs:
Overhead factorsforarea timing power source35 3.4...4.6 14 Kuon & Rose(2007, 90 nm CMOS)27 5.1 n.a. Ho et al.(2013, 130 nm CMOS)
Antifuse technology, hardwired multipliers, etc. improve the situation,buta penalty remains.
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General ideaConfiguration technologiesOrganization of hardware resources
C i l tAn overview on FPL device familiesTh i d th b fit f l t i l fi bilit
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Commercial aspectsExtensions of the basic idea
The FPL design flow
The price and the benefits of electrical configurability
The price of electrical configurability II
I Huge area overhead 7 large FPGAs continue to be rather expensive.
Figure: In an attempt to compensate for this, FPL vendors use the most advancedfabrication processes(source: Altera White Paper WP-01199).
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General ideaConfiguration technologiesOrganization of hardware resources
Commercial aspectsAn overview on FPL device familiesThe price and the benefits of electrical configurability
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Commercial aspectsExtensions of the basic idea
The FPL design flow
The price and the benefits of electrical configurability
FPL compared to semi- and full-custom ICs
circuitsize
full-customIC
productionvolume
field-programmablelogic
(FPGA or CPLD)
SSI MSI LSI VLSI ULSI
10 100 1k 10k 100k 1M1 [GE]10M 100M 1G
100
1k
10k
100k
1M
10M
semi-customIC
towards highly
(asks for commitment)optimized implementation
towards highly
(implies circuit andagile implementation
energy overheads)
two-level logic
field-
logic based on
(SPLD)
programmable
technologypush
Figure: Implementation techniques as a function of circuit complexity and volume.
I Each technique has its niche where it is the best compromise.
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General ideaConfiguration technologiesOrganization of hardware resources
Commercial aspects
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Commercial aspectsExtensions of the basic idea
The FPL design flow
Subject
Extensions of the basic idea
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General ideaConfiguration technologiesOrganization of hardware resources
Commercial aspects
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Commercial aspectsExtensions of the basic idea
The FPL design flow
Providing only as much configurability as needed
Configurable logic cells are
+ designed to implement small LUTs and random logic functions,
extremely wasteful(in terms of area, delay and energy) when usedto implementI
datapaths(that include multiplications and related arithmetic-logicoperations)on wide data words,I instruction-set processors(where the software affords flexibility), orI fixed functions(that do not ask for flexibility),
unsuitable for implementing analog subfunctions.
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pExtensions of the basic idea
The FPL design flow
Providing only as much configurability as needed
Configurable logic cells are
+ designed to implement small LUTs and random logic functions,
extremely wasteful(in terms of area, delay and energy) when usedto implementI
datapaths(that include multiplications and related arithmetic-logicoperations)on wide data words,I instruction-set processors(where the software affords flexibility), orI fixed functions(that do not ask for flexibility),
unsuitable for implementing analog subfunctions.
Second stage of evolution
FPL gets combined with less malleable but more cost-effectiveand more efficient hardware resources.
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Commercial aspects
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pExtensions of the basic idea
The FPL design flow
Some FPGAs include wide datapath units (MAC)
Figure: Example: DSP48E1 slice from Xilinx Virtex-6
(25x18bit multiply, 48bit accumulate).c Hubert Kaeslin Microelectronics Design Center ETH Zurich Field-Programmable Logic 33/46
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Extensions of the basic ideaThe FPL design flow
Some real-world numbers
Vendor XilinxProduct Virtex-7 Virtex UltrascaleYear introduced 2013 2014
Technology 20 nm CMOS 16 nm CMOSplanar finFET
Configurable logic cells [k] 1995 4407Block RAM [Mbit] 68 115DSP48 slices 3600 2880I/O pins 1200 1456Serial transceivers 96 104
PCI Express blocks 4 6100G Ethernet blocks 0 7Mem. bandwidth [Mbit/s] 1866 2400
Table: Maximum resources in two of the most advanced FPGA families.
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General ideaConfiguration technologiesOrganization of hardware resources
Commercial aspectsE i f h b i id
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Extensions of the basic ideaThe FPL design flow
Almost all FPGAs mix-in hardwired units
Common subblocks SRAMs, FIFOs, clock recovery circuits, SerDes, etc.
Industry-standard functions and interfaces such as PCI, USB, FireWire,Ethernet, WLAN, JTAG, LVDS, etc.
Analog-to-digital and digital-to-analog converters
Entire microprocessor and DSP cores (e.g. PowerPC, ARM)
Weakly configurable analog subfunctions such as filters or PLLs
Countless combinations are commercially available.
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General ideaConfiguration technologiesOrganization of hardware resources
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Extensions of the basic ideaThe FPL design flow
Almost all FPGAs mix-in hardwired units
Common subblocks SRAMs, FIFOs, clock recovery circuits, SerDes, etc.
Industry-standard functions and interfaces such as PCI, USB, FireWire,Ethernet, WLAN, JTAG, LVDS, etc.
Analog-to-digital and digital-to-analog converters
Entire microprocessor and DSP cores (e.g. PowerPC, ARM)
Weakly configurable analog subfunctions such as filters or PLLs
Countless combinations are commercially available.
And then there exist
Field-programmable analog arrays (FPAA) built from OpAmps, capacitors,resistors and switchcap elements.
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General ideaConfiguration technologiesOrganization of hardware resources
Commercial aspectsExtensions of the basic idea
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Extensions of the basic ideaThe FPL design flow
Block diagram of Cypress mixed-signal PSoC 5LP device
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General ideaConfiguration technologiesOrganization of hardware resources
Commercial aspectsExtensions of the basic idea
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Extensions of the basic ideaThe FPL design flow
Capacity figures of FPL devices may be confusing ...
Manufactured gates Total number of GEs physically present on a die.
Usable gates Maximum number of GEs that are usable under typical orbest case conditions. The exact percentage depends on the
application,advertisements tend to exaggerate.Actual gates GEs that are indeed put to service by a given design,
corresponds to the GEs for a cell-based full-custom IC.
GEmanuf >GEusable>GEactual
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General ideaConfiguration technologiesOrganization of hardware resources
Commercial aspectsExtensions of the basic idea
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Extensions of the basic ideaThe FPL design flow
Capacity figures of FPL devices may be confusing ...
Manufactured gates Total number of GEs physically present on a die.
Usable gates Maximum number of GEs that are usable under typical orbest case conditions. The exact percentage depends on the
application,advertisements tend to exaggerate.Actual gates GEs that are indeed put to service by a given design,
corresponds to the GEs for a cell-based full-custom IC.
GEmanuf >GEusable>GEactual
4 Numbers frequently muddled up in an attempt to make one product lookbetter than competition.
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General ideaConfiguration technologies
Organization of hardware resourcesCommercial aspects
Extensions of the basic idea
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The FPL design flow
... and this is just the tip of the iceberg
Certainly one of the problems with FPGA technology is that youreconstantly comparing different things. Apples and oranges, XilinxCLBs and Altera ALMs, field-programmable elements and largelyhardwired datapath units, total negative slack and fastest clock,dynamic power at 20 C and quiescent power at 85 C, prices today
for quantity 1000 and prices for 9 months from now at quantity250 000. The list is almost endless, and useful comparison data isvirtually impossible to gather. (after Kevin Morris, 2005)
Hint
Carry out benchmarks with representative designs as this helps toI make better cost calculations,
I obtain realistic timing figures,
I avoid misguided choices.
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General ideaConfiguration technologies
Organization of hardware resourcesCommercial aspects
Extensions of the basic idea
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The FPL design flow
Subject
The FPL design flow
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General ideaConfiguration technologies
Organization of hardware resourcesCommercial aspects
Extensions of the basic idea
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The FPL design flow
FPL design flow
Front-end is essentially the same as for ASICs:
1. Architecture design.2. HDL coding.3. Functional verification(mostly by way of simulations).4. HDL synthesis 7 Gate-level netlist.
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General ideaConfiguration technologies
Organization of hardware resourcesCommercial aspects
Extensions of the basic ideaTh FPL d i fl
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The FPL design flow
FPL design flow
Front-end is essentially the same as for ASICs:
1. Architecture design.2. HDL coding.3. Functional verification(mostly by way of simulations).4. HDL synthesis 7 Gate-level netlist.
Back-end differs considerably.
5. Gate-level netlist is mapped onto the configurable cellsavailable in the target device.
6. Interconnect gets implemented using the wires,switches and drivers available there.
7. Result is converted into aconfiguration bit streamfor download into the FPL device.
FPL vendors make available proprietary tools.
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Extensions of the basic ideaTh FPL d si fl
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Particularities of coarse-grained FPGAs
Look-up tables cheapand typically avail in chunks of 64 entries. Routing dominates over gate delaydue to conf. switches and larger die.
Routing resources limited.
+ Flip-flops come in generous numbers pipelining is essentially free.
One-hot, Gray, or Johnson encoding sometimes better than min. bit count.
+ On-chip clock preparation circuits (nets, drivers, PLLs).
Asynchronous reset compete for global interconn. resources with clocks.
+ Sophisticated input/output circuits(adjustable, LVDS, synchronization).
+ On-chip block RAMs(depending on product).
+ Many parts include weakly configurable datapath units.
Datapaths, multipliers, adders, and memories come with fixed widths.
+ Available with on-chip microcontroller(depending on product).
Parts come in fixed sizes.
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General ideaConfiguration technologies
Organization of hardware resourcesCommercial aspects
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The FPL design flow
FPL versus ASIC design
Advice
The cost matrix is not the same as for ASICs. Be aware of the realities
of the target platform before writing RTL synthesis code.
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General ideaConfiguration technologies
Organization of hardware resourcesCommercial aspects
Extensions of the basic ideaThe FPL design flow
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The FPL design flow
FPL versus ASIC design
Advice
The cost matrix is not the same as for ASICs. Be aware of the realities
of the target platform before writing RTL synthesis code.
Hierarchy of required skill sets
Field-programmable logic Semi-custom ICs Full-custom ICs
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The FPL design flow
What keeps designers awake at night
mapping on target device
this volume
manufacturing andtesting partners
power distribution
process migration
testability
electrical overstressprotection
clock distribution
I/O subcircuits
process and libraryselection
macrocell generation
floorplanning,place and route
integration ofvirtual components
ASIC design
granularities
limited and slowrouting resources
platform selection
limited package optionsand pinout constraints
bit stream preparation
FPL design
product-dependent
functional verification
HDL modeling
architecture design
synchronization
HDL synthesis
clock domains
Figure: Primary concerns of FPL customers and full-custom ASIC designers.
The VLSI I course covers those topics that matter independently of fabrication depth,
VLSI II and III then specialize on ASIC design and VLSI technology.
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g
Pros and cons of field-programmable logic
+ Easy and extremely fast to modify(in minutes instead of months).
+ Designers can focus on functionality right away.No need to agonize over subordinate details such asI I/O subcircuits,I
clock distribution,I power distribution,I embedded memories,I testability, etc.
+ Low initial effort, lower than any other hardware alternative.
+ Affordable design tools.
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Pros and cons of field-programmable logic
+ Easy and extremely fast to modify(in minutes instead of months).
+ Designers can focus on functionality right away.No need to agonize over subordinate details such asI I/O subcircuits,I clock distribution,I power distribution,I embedded memories,I testability, etc.
+ Low initial effort, lower than any other hardware alternative.
+ Affordable design tools.
Devices come in thousands of variations, may be confusing.
Huge overheadin terms of area, delay(performance), and energy.
Cost-effective for small volumes, not economic for large quantities.
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Conclusions
Field-programmable logic is ideal for
I Prototypingand other
I Situations wherespecs are subject to changeat any time
I Products that sell inmodest quantities,
I Products wheretime to market is paramount,
I Products that need to bereconfigured or updated from remote.
Cost structure to be examined in chapter 16 VLSI Economics and Project Management.
I Owing to their more scalable and flexible organization,FPGAs prevail over CPLDs.
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Outlook
I The trend towards (re)configuring larger, more powerful entities(ALUs, datapath units, memories, etc. rather than gates and LUTs)
I and towards mixingI reconfigurable logic withI processor cores andI fixed function blocks
is expected to continue.
This will naturally lead to the concept ofplatform ICs
as a next stage of evolution for FPL.
To be introduced in chapter 3 From Algorithm to Architectures.
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