FPGA signal processing: digital filters santa clara universityDigital Filters v4.1 © Chris Dick...

Digital Filters v4.1 © Chris Dick 2009 1

FPGA signal processing: digital filters

santa clara university

dr chris dick

dsp chief architect

wireless and signal processing group

xilinx inc.

Digital Filters

• Digital filter review

• multirate filters

– polyphase decimators

– polyphase interpolators

• Distributed Arithmetic

• FPGA implementation

Digital Filters: Review

• What design parameters define

– filter length

– side-lobe level

2Na − 1Na −

x n( )

y n( )

( )( )

Y zH z a z

−−

= =∑

( ) ( ) ( 1) ( ( 1))

y n a x n a x n a x n N

a x n i

= + − + − −

= −∑

1−δ11

−δ2

|H(ejΩ)|

PASSBAND

STOPBAND

TRANSITION BAND

• No analytic solution for computing FIR filter length

• Approximations

– Kaiser

– Bellanger

– Hermann

– fred harris

f∆∼

2 1 1log

3 10Approximation due to Bellanger N

fδ δ

≈ ⋅ ⋅

10 1 220log 131

14.6Approximation due to Kaiser N

δ δ− −≈ +

(, 20 log

dB)Approximation due to fred harris (dB)sf A

δ≈ ⋅ = ⋅∆

( ) 0.922 20

transition width

Attenuation (dB) Attenuation (dB)

Attenuation (dB)

now solve for

Attenuation (dB)

ff K A

∆ ⇒

= = ⋅

∆ = ⋅

= ⋅∆

Quantizing the filter

The stopband attenuation is a strong function of the coefficient

precision

Approximately 5 dB of stopband attenuation is per bit of coefficient

precision

60 dB sidelobes will require 12-bit

B B A∝

∼ precision coefficients

90 dB sidelobes will require 18-bit precision coefficients∼

Examplesample rate fs = 1 Hz

passband ripple: 0.1 dB

stopband ripple: 96 dB

passband edge frequency 0.1 Hz

stopband edge frequency = 0.14 Hz

Filter Design

Matlab fdatool

0 20 40 60 80 100-0.1

Frequency (MHz)

F loating Point

0 0.05 0.1-0.2

Frequency (MHz)

0 0.5-60

Frequency (MHz)

0 0.05 0.1-0.2

Frequency (MHz)

0 0.05 0.1-0.2

Frequency (MHz)

0 0.5-80

Frequency (MHz)

B = 12

0 0.05 0.1-0.2

Frequency (MHz)

B = 12

Frequency (MHz)

B = 10

0 0.05 0.1-0.2

Frequency (MHz)

B = 10

0 0.5-100

Frequency (MHz)

B = 16

0 0.05 0.1-0.2

Frequency (MHz)

B = 16

Frequency (MHz)

B = 14

0 0.05 0.1-0.2

Frequency (MHz)

B = 14

Multirate Filters

One of the most important aspects of digital filter

architecture for a communication and signal processing engineer is multirate filters

x(n) y(n)MATCHED FILTER

IBBx(n)

P. P. Vaidyanathan, Multirate Systems and Filter Banks Prentice Hall, Englewood Cliffs, New

Jersey, 1993

Decimation

Mx n( ) y nD ( )

x n( )y nD ( )0

y nD ( )x n( )

x n( )

y nD ( )

Interpolation

Lx n( ) y nE ( )

x n( )0

x n( )

y nE ( )

x n( )

L y nE- fold rate expanded sequence ( )

The Noble Identities

P. P. Vaidyanathan, Multirate Systems and Filter Banks Prentice Hall, Englewood Cliffs, New Jersey, 1993

H(zM) MX(z) Y(z) H(z)MX(z) Y(z)

H(zL)LX(z) Y(z) H(z) LX(z) Y(z)

The Noble Identities are essential to the understanding of multirate filter

techniques

Multirate Filters: Spectral View

P. P. Vaidyanathan, Multirate Systems and Filter Banks Prentice Hall, Englewood Cliffs, New Jersey, 1993

0 2π2π−

( )jX e

0 2π2π−

Expander L = 5

0 2π2π−

ππ−

2 / Lπ2 / Lπ−

π− π

Decimator M = 2

Spectral Images

Aliasing

Multirate Filters• FDM Communication System

we are motivated to reduce the sample rate so that the down-stream

processing can be operated at the lowest sample rate possible

• minimize the arithmetic workload requirements• this will reduce

- clock cycles in a soft DSP implementation- silicon resources + possibly power in an FPGA realization

1 MHz-1 MHz

fs = 100 MHz

H(z) Mx(n) y(n)

anti-aliasing filter down sampler

Polyphase Decimator

There is an obvious inefficiency here

For each sample delivered to the filter H(f) an output sample is computed and yet

only 1 in M of these samples survive the re-sampling operation

We must optimize the structure so that only those output samples that are

retained in the decimation process are computed by the filter

Also note that the filter hardware is operating at the higher input sample rate

H(z) Mx(n) y(n)

Polyphase Representation by Induction

x n( )

y n( )

y nD ( )

y x h x h y

y x h x h x h

y x h x h x h x h y

y x h x h x h x h

y x h x h x h x h y

y x h x h x h x h

y x h x h x h x h y

1 1 0 0 1

2 2 0 1 1 0 2

3 3 0 2 1 1 2 0 3

4 4 0 3 1 2 2 1 3

5 5 0 4 1 3 2 2 3

6 6 0 5 1 4 2 3 3

7 7 0 6 1 5 2 4 3

= + + + =

= + + +

= + + + =

= + + +

= + + + =

Polyphase Representation by Induction

y nD ( )

x n( )

yD ( )0

x n( )

y x h x h y

y x h x h x h

y x h x h x h x h y

y x h x h x h x h

y x h x h x h x h y

y x h x h x h x h

y x h x h x h x h y

1 1 0 0 1

2 2 0 1 1 0 2

3 3 0 2 1 1 2 0 3

4 4 0 3 1 2 2 1 3

5 5 0 4 1 3 2 2 3

6 6 0 5 1 4 2 3 3

7 7 0 6 1 5 2 4 3

= + + + =

= + + +

= + + + =

= + + +

= + + + =

Polyphase Representation by Inductionx( )3

yD ( )1

x n( )

y x h x h y

y x h x h x h

y x h x h x h x h y

y x h x h x h x h

y x h x h x h x h y

y x h x h x h x h

y x h x h x h x h y

1 1 0 0 1

2 2 0 1 1 0 2

3 3 0 2 1 1 2 0 3

4 4 0 3 1 2 2 1 3

5 5 0 4 1 3 2 2 3

6 6 0 5 1 4 2 3 3

7 7 0 6 1 5 2 4 3

= + + + =

= + + +

= + + + =

= + + +

= + + + =

yD ( )2

x n( )

Polyphase Decimator

Now build the structure described by the equation and then apply the

Noble Identities

H(z) Mx(n) y(n)

4 40 1

( 1)/4 ( 1)/4 ( 1)/4 ( 1)/44 (4 1) (4 2) (4 3)

0 0 0 0

( 1)/4 ( 1)/44 1 4 2

( ) ( )

(4 ) (4 1) (4 2) (4 3)

(4 ) (4 1)

N N N Nn n n n

n n n n

N Nn n

H z H z

H z h n z

h n z h n z h n z h n z

h n z z h n z z

−−

− − − −− − + − + − +

= = = =

− −− − − −

= + + + + + +

= + + +

∑ ∑ ∑ ∑

∑ ∑

4 42 3

( 1)/4 ( 1)/44 3 4

( ) ( )

4 1 4 2 4 3 4

0 1 2 3

(4 2) (4 3)

( ) ( ) ( ) ( )

N Nn n

H z H z

h n z z h n z

H z z H z z H z z H z

− −− − −

− − −

= + + +

∑ ∑

For M = 4

Polyphase Decimator

H(zM) MX(z) Y(z) H(z)MX(z) Y(z)

0 ( )H z−

1( )H z−

2 ( )H z−

3 ( )H z−

0 ( )H z−

1( )H z−

2 ( )H z−

3( )H z−

0 ( )H z−

1( )H z−

2 ( )H z−

3( )H z−

There are some errors in these diagrams: the H0(z-4),

H1(z-4), H2(z

-4) and H3(z-4) in these figures should be just

H0(z4), H1(z

4), H2(z4) and H3(z

4) respectively. The terms H0(z-1),

H1(z-1), H2(z

-1) and H3(z-1) should just read H0(z), H1(z), H2(z) and

H3(z) respectively.

Polyphase Decimator

n-3 n-2 n-1 n n+1 n+2 n+3n+4

n-4 n-3 n-2 n-1 n n+1 n+2n+3

n-5 n-4 n-3 n-2 n-1 n n+1 n+2

n-6 n-5 n-4 n-3 n-2 n-1 n n+1

1z− 4

2z− 4

3z− 4

n-3 n-2 n-1 n n+1 n+2 n+3 n+4

n-4 n-3 n-2 n-1 n n+1 n+2 n+3

n-5 n-4 n-3 n-2 n-1 n n+1 n+2

n-6 n-5 n-4 n-3 n-2 n-1 n n+1

( )x n

( 1)x n −

( 2)x n −

( 3)x n −

Polyphase Decimator

0 ( )H z−

1( )H z−

2 ( )H z−

3 ( )H z−

Each polyphase segment operates at the lower output sample rate

( )x n( )Dx n

There are some errors in these diagrams: The terms

H0(z-1), H1(z

-1), H2(z-1) and H3(z

-1) should just read H0(z), H1(z),

H2(z) and H3(z) respectively.

Spectral View0.25

M=40 0.25 0.5 10.75-0.25-0.5-1 -0.75

0 0.25 0.5 10.75-0.25-0.5-1 -0.75f

0 1 2 3

Spectral View

Now reduce the sample rate to match the filtered signal’s BW

0 0.5 1-0.5-1

ff ′ =

Example 1 (1)

Filtering when the bandwidth is much smaller than the sample rate

+ fs− fs

s= ⋅

20 000

Prototype Spectrum Image SpectrumImage Spectrum

A(dB) = dB

Example 1 (2)

Prototype Spectrum

Replicate

Spectrum at

Input Rate

Lowpass

Filter

fs = 20 kHz fs = 20 kHz

100 300 400

100 Hz Bandwidth

Replicate

Spectrum at

Output Rate

Spectral shift

from multirate

filter

Example 1 (3)

Lowpass

Filterfs = 20 kHz fs = 20 kHz

100 Hz Bandwidth, 364 taps 364 FOPs/Output = 364 FOPs/Input

FOP = Filter Operation

50:1Downsample

Filter

20 kHz

364 taps

50:1Upsample

Filter50:1

20 kHz

364 taps

Single rate solution

Multirate solution

Example 1 (4)

20 kHz

For convenience make the prototype

filter length 400 taps, each polyphase

segment has taps

400 FOPs @ 400 Hz 8 FOPs / Input

H49(z)

20 kHz 400 Hz

8 FOPs/Output8 FOPs/Input

The net compute load is

FOPs / Output

single rate soln: 400 FOPs / Output

Example 2 (1)

• The task is to generate shaped noise

Filter Specifications

Sample rate = kHz

Passband = 0.00 0.10 kHz

Stopband = 0.30 0.50 kHz

Stopband attentuation = dB

Filter Length =

20 000

⋅ =,

Generator

Lowpass

Filter

N = 364

20 kHz 20 kHz

Example 2 (2)Input Noise

ffs = 20 kHz

Filter Response

fs = 20 kHz

Filtered Noise

fs = 20 kHz

20 kHz

H49(z)

8 FOPs/Output

Generator

0.40 kHz

Input Noise

fs = 20 kHz

Filter Response

fs = 20 kHz

Filtered Noise

fs = 20 kHz

Interpolation: Motivation

ADCDigital

Receiver

All digital receiver

Asynchronous sampling wrt to

modulation waveform baud timing

Raw samples from ADC

Receiver requires access to intermediate sample positions

Interpolation L=2

a0 a1 a2 a3 a4 a5

x(0) 0 0 0 0 0

a0 a1 a2 a3 a4 a5

x(0)0 0 0 0 0

a0 a1 a2 a3 a4 a5

x(1) 0 0 0 0x(0) x(n)

a0 a1 a2 a3 a4 a5

x(1)0 0 0 0x(0)

a0 a1 a2 a3 a4 a5

x(2) 0 0 0x(1) x(n)

a0 a1 a2 a3 a4 a5

x(1)0 00 x(0)

x(0) x(2)

(e) (f)

Interpolation

• Only a subset of the coefficients are used to compute y(n)

• In this architecture the convolver is operating at the high

output sample rate

• This process can be replaced by multiple independent

convolvers at the lower input rate so removing redundant

multiplications

Interpolation

H(z)5X(z) Y(z)

( 1)/5 ( 1)/5 ( 1)/5 ( 1)/5 ( 1)/54 (5 1) (5 2) (5 3) (5 4)

0 0 0 0 0

( 1)/55 1 5

( ) ( )

(5 ) (5 1) (5 2) (5 3) (5 4)

(5 ) (5 1)

N N N N Nn n n n n

n n n n n

H z h n z

h n z h n z h n z h n z h n z

h n z z h n z

−−

− − − − −− − + − + − + − +

= = = = =

−− − −

= + + + + + + + +

∑ ∑ ∑ ∑ ∑

5 5 5 51 2 3 4

( 1)/5 ( 1)/5 ( 1)/5 ( 1)/52 5 3 5 4 5

( ) ( ) ( ) ( )

5 1 5 2 5 3 5 4 5

0 1 2 3 4

(5 2) (5 3) (5 4)

( ) ( ) ( ) ( ) ( )

N N N Nn n n

H z H z H z H z

z h n z z h n z z h n z

H z z H z z H z z H z z H z

− − − −− − − − − −

− − − −

+ + + + + +

= + + + +

∑ ∑ ∑ ∑

For L = 5

Now build the structure described by the equation and then apply the

Noble Identities

Interpolation5

0 ( )H z−

1( )H z− 1z−

2 ( )H z− 2z−

3( )H z− 3z−

4 ( )H z− 4z−

0 ( )H z−

1( )H z− 1z−

2 ( )H z− 2z−

3( )H z− 3z−

4 ( )H z− 4z−

5There are some errors in these diagrams: the H0(z

-5), H1(z-5),

H2(z-5) , H3(z

H0(z5), H1(z

5), H2(z5) H3(z

5) and H4(z5) respectively.

Interpolation

0 ( )H z−

1( )H z− 1z−

2 ( )H z− 2z−

3( )H z− 3

4 ( )H z− 4z−

H(zL)L H(z) L

Recall the Noble identity

Apply it to the previous figure to produce

There are some errors in these diagrams: the H0(z-1), H1(z

H2(z-1) , H3(z

H0(z1), H1(z

1), H2(z1) H3(z

Interpolation

0 ( )y n

1( )y n

2 ( )y n

3( )y n

4 ( )y n

0ˆ ( )y n

1ˆ ( )y n

2ˆ ( )y n

3ˆ ( )y n

4ˆ ( )y n

0ˆ ( )y n

1ˆ ( 1)y n −

2ˆ ( 2)y n −

3ˆ ( 3)y n −

4ˆ ( 4)y n −

( 5)y kn +

ˆ ( )y n0

ˆ ( )y n

ˆ ( 1)y n −1

ˆ ( )y n

ˆ ( 2)y n −2

ˆ ( )y n

ˆ ( 3)y n −3

ˆ ( )y n

ˆ ( 4)y n −4

ˆ ( )y n

( 5)y kn +

Interpolation1

0 ( )H z−

1( )H z−

2 ( )H z−

3( )H z−

4 ( )H z−

L filter operations at the low input sample rate

polyphase architecture is 1/Lth the processing load

this will often make the difference between being able to implement a

system or not

large convolution sum replaced with multiple convolutions operating at

the low input sample rate

sf5 sf⋅

( )x n( )Ix n

There are some errors in these diagrams: the H0(z-1), H1(z

H2(z-1) , H3(z

H0(z1), H1(z

1), H2(z1) H3(z

Filters in Virtex-4/5/6

• Examine

– Basic single rate structures

– Multirate filter implementations

FIR Filter• Single time division multiplexed MAC

– Folding factor = N (num. filter coefficients)

Parameters Area fclk (MHz) fs (MHz)

LUT/FF Slices BRAM DSP48

N = 240 nFU = 1 16b data 16b coefficients

38/172 74 1 1 500 ~2

ISE 9.2.03; XST; par –ol high; Speed File 1.57; Virtex-5 XCVSX35T-3

SRL Timing

• Illustration of SRL timing in FIR filter

x(0), 0, 0, 0

Select

3n Clock cycle n

Select

3n Clock cycle n

x(1), x(0), 0, 0

Select

3n Clock cycle n

x(2), x(1), x(0), 0

Select

3n Clock cycle n

x(3), x(2), x(1), x(0)

FIR Filter• Single time division multiplexed

– Folding factor = N (num. filter

coefficients)

– Data: SRL

– Coefficient storage: distributed

memory

• LUT memory good choice for short

filters

– Minimizes inefficient use of BRAM

57/240 88 0 1 500 ~31.25

Detailed Look At Filter Timing

• DSP48 based FIR Filter

Document ID: mWS4jvW3

Pipelined FIR FilterInput sample rate = 550 MHz, Coefficients = 4

Regressor vector implemented

using DSP48 internal registers

Max Sample Rate = Clock Rate

Dedicated cascade connections (PCOUT and PCIN) are exploited to

achieve maximum performance

ACIN/ACOUT ports on DSP48E used

to support high-speed interconnection in regressor

vector path

K0 K1 K2 K3

DSP48 Slice

opmode = 0010101

DSP48 Slice

opmode = 0000101

Symmetric Pipelined FIR Filter

Input width must

be no more than

17 bits due to the

pre-adder

FPGA footprint:

4 XDSP Slice

72 SlicesMax Filter Sample Rate = Clock Rate

No more pipelining is required here for the

folded structure due to the pipeline stages in

the adder chain

9 9 9 9

Virtex4 & Virtex 5: Regressor vector storage is realized using FPGA logic fabric to support the use of a pre-addition which is also realized in the FPGA fabric

Virtex-6, Spartan-6, Spartan 3A: have the pre-adder incorporated in the DSP slice

Folded FIR

f nFUf

146/344 123 0 5 550 550/3 ~ 183.3

Figure shows N=16 and nFU = 4

Polyphase Interpolator

• Single MAC polyphase interpolator

L = 4 N = 40 nFU = 1 16b data 16b coefficients

91/270 101 0 1 550 55

1 functional unit time division multiplexed across all MAC operations Datapath identical to polyphase decimator

Control/addressing is different

Polyphase Interpolator

• Multi-MAC polyphase interpolatorclk

f L nFUf

⋅ ⋅=

L = 4 N = 40 nFU = 4 16b data 16b coefficients

160/382 131 0 5 550 220

Polyphase Decimator

• Single MAC polyphase decimator

M = 4 N = 40 nFU = 1 16b data 16b coefficients

88/213 90 0 1 550 55

1 functional unit time divisionMultiplexed across all MAC operations in each of the 4 polyphase segments

Multi-functional Unit Polyphase Decimator

f nFU Mf

⋅ ⋅=

146/344 123 0 5 550 550

Each of the 4 MACs process 10 / 4 3

coefficients in each segment

Timing For Polyphase Decimator (1)

The diagram on the left is the

‘MAC Cell 1’ in the earlier

diagram of the polyphase

filter

Timing For Polyphase Decimator (2)

• Timing for the 2nd MAC unit

FPGA signal processing: digital filters santa clara universityDigital Filters v4.1 © Chris Dick...

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