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FPGA Design with FPGA Design with XilinxXilinxISEISE

Presenter: Shu-yen LinAdvisor: Prof. An-Yeu Wu

2005/6/6

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OutlineOutlinevConcepts of Xilinx FPGAvXilinx FPGA ArchitecturevIntroduction to ISEvCode GeneratorvConstraints and ReportsvConfigurationvDemo and Lab

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Concepts of Concepts of XilinxXilinx FPGAFPGA

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Electronic ComponentsElectronic Components

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FPGA BenefitsFPGA Benefits

●●Educational Purpose

●●●●●Development Tool

●●Future Modification

●●Risk Reduction

●●●Time to Market

●●●Low-Volume device Cost

●●●●●●High-Volume Device Cost

●●●●●Integration Density

●●●●●Speed

FPGAGate ArraysCell-Based ICs

Full-Custom ICs

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Full Full XilinxXilinx Design SupportDesign Support

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Xilinx Products v CPLDs and FPGAs

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XilinxXilinx FPGA ArchitectureFPGA Architecture

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The Conceptual CPLD ArchitectureThe Conceptual CPLD Architecture

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The Conceptual FPGA ArchitectureThe Conceptual FPGA Architecture

v Field-programmablev Re-programmablev In-circuit design verificationv Rapid prototypingv Fast time-to-marketv No IC-test & NRE costv H/W emulation instead of S/W

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SpatranSpatran--2/2E, 2/2E, VirtexVirtex / / VirtexVirtex--E FPGA Architecture (1/6)E FPGA Architecture (1/6)

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v Logic and Routing - the CLB tileSpatranSpatran--2/2E, 2/2E, VirtexVirtex / / VirtexVirtex--E FPGA Architecture (2/6)E FPGA Architecture (2/6)

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SpatranSpatran--2/2E, 2/2E, VirtexVirtex / / VirtexVirtex--E FPGA Architecture (3/6)E FPGA Architecture (3/6)

v Two slices in each CLBv Each slice contains 2 LUT, 2 Register and 2 Carry Logic.

vLogic and Routing – Simplified CLB Structure

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SpatranSpatran--2/2E, 2/2E, VirtexVirtex / / VirtexVirtex--E FPGA Architecture (3/6)E FPGA Architecture (3/6)

v Logic and Routing – Look-Up Tables (LUTs)v Combinational logic is stored in Look-up Tables

(LUTs) in a CLB.v Capacity is limited by number of inputs, not

complexity.v Delay through CLB is constant.

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SpatranSpatran--2/2E, 2/2E, VirtexVirtex / / VirtexVirtex--E FPGA Architecture (4/6)E FPGA Architecture (4/6)

v System Interface – Select IOTM

v Supports multiple voltage and signal standards simultaneouslyv Eliminate costly bus transceivers

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v System Memory – Distributed RAM, Block RAM and External MemorySpatranSpatran--2/2E, 2/2E, VirtexVirtex / / VirtexVirtex--E FPGA Architecture (5/6)E FPGA Architecture (5/6)

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SpatranSpatran--2/2E, 2/2E, VirtexVirtex / / VirtexVirtex--E FPGA Architecture (6/6)E FPGA Architecture (6/6)

v System clock management - DLLsv Clock MirrorvMultiplicationØ 1 DLL for 2xØCombine 2 DLL for 4x

v DivisionØ Selectable division values - 1.5, 2, 2.5,

3, 4, 5, 8, or 16v Phase ShiftØ 0, 90, 180, 270

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SpatranSpatran--3, 3, VirtexIIVirtexII FPGA Architecture (1/7)FPGA Architecture (1/7)

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SpatranSpatran--3, 3, VirtexIIVirtexII FPGA Architecture (2/7)FPGA Architecture (2/7)v Logic and Routing - the CLB tile

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SpatranSpatran--3, 3, VirtexIIVirtexII FPGA Architecture (3/7)FPGA Architecture (3/7)vSystem Interface – Select IOTM 23 different

standards supported !

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SpatranSpatran--3, 3, VirtexIIVirtexII FPGA Architecture (4/7)FPGA Architecture (4/7)v System Memory –External Memory supports DDR memory

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SpatranSpatran--3, 3, VirtexIIVirtexII FPGA Architecture (5/7)FPGA Architecture (5/7)v System clock management – DCMs

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SpatranSpatran--3, 3, VirtexIIVirtexII FPGA Architecture (6/7)FPGA Architecture (6/7)v System clock management – DCMs

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SpatranSpatran--3, 3, VirtexIIVirtexII FPGA Architecture (7/7)FPGA Architecture (7/7)v Embedded multiplexer

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VirtexIIVirtexII Pro FPGA ArchitecturePro FPGA Architecture

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Programmable Logic EvolutionProgrammable Logic Evolution

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Introduction to ISEIntroduction to ISE

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ISE PhilosophyISE Philosophyv ISE 6.1iv Future Xilinx devicesv Proactive Timing Closurev ECS & HDL Bencher & XST

v Platformv Unix: Solaris 2.7/2.8v PC: Win 2000/XP

v Service Packv http://support.xilinx.com

v ISE WebPagev http://www.xilinx.com/ise

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Design Flow in ISE (1/2)Design Flow in ISE (1/2)

Design

Synthesis

Implement

Download

A & B = C

AB

C

LUT RegAB

C

CLB

AB

C

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Design Flow in ISE (2/2)Design Flow in ISE (2/2)

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Introduction to Projection Navigator (1/4)Introduction to Projection Navigator (1/4)

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Introduction to Projection Navigator (2/4)Introduction to Projection Navigator (2/4)v Source Windows

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Introduction to Projection Navigator (3/4)Introduction to Projection Navigator (3/4)vProcesses for current source

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Introduction to Projection Navigator (4/4)Introduction to Projection Navigator (4/4)v Processes for current source

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Create New ProjectCreate New Project

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Create New SourceCreate New Source

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HDL Source FileHDL Source File

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Text EntryText Entry

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Language TemplatesLanguage Templates

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Synthesis (1/4)Synthesis (1/4)v XST

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Synthesis (2/4)Synthesis (2/4)v XST Flow

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Synthesis (3/4)Synthesis (3/4)v Synthesis Step

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Synthesis (4/4)Synthesis (4/4)v RTL view

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Implementation (1/8)Implementation (1/8)

Translate - Merge multiple design files into a single netlistMap - Group logical symbols from the netlist (gates) into physical components (CLBs and IOBs)Place & Route - Place components onto the chip, connect them, and extract timing data into reports

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Implementation (2/8)Implementation (2/8)

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TranslateImplementation (3/8)Implementation (3/8)

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MapImplementation (4/8)Implementation (4/8)

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Implementation (5/8)Implementation (5/8)

vMap Propertyv Trim Unconnected SignalsØ If you check this item, the mapping tool will remove the unconnected

wire that let the tracing back become hardly.v Generate Detailed Map ReportØ If more detailed report is needed, you can check it. (Recommending

check it)v Use Guide Design File (.ncd)Ø You can refer the last mapping solution so that you maybe get better

solution. v Use RLOC ConstraintsØConstraints of CLB (default check).

v Pack I/O Registers/Latches into IOBsØ If the value chosen Default that pack the register nearby I/O into I/O

block. You can also chose only for input or only for output or off.

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Place and Route

Implementation (6/8)Implementation (6/8)

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v Place and Route Property (1/2)v Place & Route Effort Level (Overall)Ø Effort Level means the P&R effect result. Using the Higher get the

better solution, but spend more time. v Starting Placer Cost Table (0-100)Ø Specify a placement initialization value with which to begin P&R

attempts. Each subsequent attempt is assigned an incremental value based on the placement initialization value.

v Place and Route ModeØQuick means without timing constraints; Route Only and Re-entrant

Route mean P&R must have been run at last once to use this option.v Guide FileØ Include the .ncd file.

Implementation (7/8)Implementation (7/8)

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v Place and Route Property (2/2)v Use Timing ConstraintsØ Include the .ucf file.

v Use Bonded I/OsØ If it is checked, signals will be connected to I/O pads.

v Generate Detailed PAR ReportØCheck the value to generate a detailed PAR report.

v Generate Post-Place & Route Static Timing ReportØCheck the value to generate post-place & route static timing report.

v Generate Post-Place & Route Simulation ModelØCheck it for generating required simulation files for ModelSim (*.v and

*.sdf).

Implementation (8/8)Implementation (8/8)

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Download (1/2)Download (1/2)

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Download (2/2)Download (2/2)

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Code GeneratorCode Generator

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What are Cores?What are Cores?

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Benefits of Using CoresBenefits of Using Cores

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Invoking the CORE Generator GUIInvoking the CORE Generator GUI

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XilinxXilinx Code Generator System GUICode Generator System GUI

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Core Customize WindowCore Customize Window

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Core Data SheetCore Data Sheet

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Core Generator Design Flow Core Generator Design Flow

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Link with Link with CodeGenCodeGen IP (IP (VerilogVerilog))

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Constraints and ReportsConstraints and Reports

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TopicsTopicsvAssign Package Pins (PACE)vAssigning Pins

vCreate Timing ConstraintsvThe PERIOD ConstraintsvThe Pad-to-Pad ConstraintsvThe OFFSET ConstraintsvThe Constraints Editor

vRead Report

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Constraints GUI (1/2)Constraints GUI (1/2)

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Constraints GUI (2/2)Constraints GUI (2/2)

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Assign Package Pins (1/6)Assign Package Pins (1/6)vStart PACE Editor

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Assign Package Pins (2/6)Assign Package Pins (2/6)vPACE Editor GUI

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Assign Package Pins (3/6)Assign Package Pins (3/6)vMethod #1 to assign package pins

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Assign Package Pins (4/6)Assign Package Pins (4/6)vMethod #2 to assign package pins

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Assign Package Pins (5/6)Assign Package Pins (5/6)vMethod #3 to assign package pins

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Assign Package Pins (6/6)Assign Package Pins (6/6)vMethod #4 to assign package pins

vUse text editor to edit .ucf filesvNET is port namevLOC assign pins to

specific location

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The PERIOD ConstraintThe PERIOD Constraint

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The PadThe Pad--toto--Pad ConstraintPad Constraint

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The OFFSET ConstraintThe OFFSET Constraint

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The Constraint Editor (1/3)The Constraint Editor (1/3)

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The Constraint Editor (2/3)The Constraint Editor (2/3)v Enter PERIOD and Pad-to-Pad Constraint

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The Constraint Editor (3/3)The Constraint Editor (3/3)v Enter OFFSET Constraint

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Read Report (1/12)Read Report (1/12)v Create Report Files

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Read Report (2/12)Read Report (2/12)

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Read Report (3/12)Read Report (3/12)v Example of MAP Report (1/2)

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Read Report (4/12)Read Report (4/12)v Example of MAP Report (2/2)

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Read Report (5/12)Read Report (5/12)

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Read Report (6/12)Read Report (6/12)v Example of PAR Report (1/2)

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Read Report (7/12)Read Report (7/12)v Example of PAR Report (2/2)

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Read Report (8/12)Read Report (8/12)

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Read Report (9/12)Read Report (9/12)v Example of Timing Report (1/4)

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Read Report (10/12)Read Report (10/12)v Example of Timing Report (2/4)

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Read Report (11/12)Read Report (11/12)v Example of Timing Report (3/4)

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Read Report (11/12)Read Report (11/12)v Example of Timing Report (4/4)

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PostPost--layout Simulationlayout Simulation

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ConfigurationConfiguration

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What is configuration?What is configuration?v Process for loading into the FPGA

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Configuration Mode (1/4)Configuration Mode (1/4)

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Configuration Mode (2/4)Configuration Mode (2/4)v Serial Mode

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Configuration Mode (3/4)Configuration Mode (3/4)vSelectMAP Mode

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Configuration Mode (4/4)Configuration Mode (4/4)v JTAG or Boundary Scan

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IMACT (1/3)IMACT (1/3)

Must double clock “Generate Programming File”before programming FPGA

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IMACT (2/3)IMACT (2/3)

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IMACT (3/3)IMACT (3/3)