Post on 17-Dec-2015
Filter designfrom Σ-Δ ADC to incremental Σ-Δ ADC
Donglijun 2013-4-28TJU ASIC center
index
filter design of Σ-Δ ADC
filter design of incremental Σ-Δ ADC
difference between the two filters
filter design of Σ-Δ ADC
• Σ-Δ ADCs are widely used in telecommunication and multimedia applications.
• The key property of Σ-Δ ADC• ①to achieve high resolution do not rely
on precisely matched analog elements • ②rely on oversampling, noise-shaping
and digital post-filtering. • ③can be integrated well into today’s
fine line-width CMOS technologies.
filter design of Σ-Δ ADC• Modulators of Σ-Δ ADC push the noise from low frequency rate
to high frequency rate. So to achieve high resolution, the key point of Σ-Δ ADC is its digit filter’s suppression of high frequency.
• The function of the filter are as follow:• ①filtering• ②decimating• ③coding• There is some parameters • for Σ-Δ ADC filter:• ①decimating rate(D)• ②bandwidth• ③SNR
A normal architecture for Σ-Δ ADC filter
CIC filterHalf-band
filterFIR
fs fs/32 fs/64 fs/128Modulator
output1bit
Digitaloutput16bits
Filter architecture
CIC filter FIR filter(half band filter)
Fir example
H(1) 1.94
H(2) -0.19
H(3) -0.25
H(4) 0
H(5) -0.25
H(6) -0.19
H(7) 1.94
bandpass example
H(1) 1.5
H(2) 0
H(3) -0.25
H(4) 0
H(5) -0.25
H(6) 0
H(7) 1.5
Introduction to incremental Σ-Δ ADC
• Unfortunately, these classical ΣΔ structures are not well suited for instrumentation and measurement (DC) applications.
• Require:• ①very high absolute accuracy and linearity• ②high dynamic range and signal-to-noise
ratio• ③Hertz wide bandwidth(nearly DC input)
u dout
比较器
Reset
1
11
z
z
积分器
Reset
1
11
z
z
积分器
Reset
2
1
1
1 z
滤波器
Reset
1
1
1 z
滤波器
diV1 V2
Filter design for IDC
3 Typical structure of decimation filter
CoI filter Sinc filter(CIC) Optimal filter
Line frequency noise S/H and the error of S/H Periodic noise suppression digit filter
Canceling periodic noise
Typical structure for IDC filter
CoI filterCascade Of Integrated
Sinc filter(CIC)Cascade Integrate Comb
Weighting factor and cycle number
Specifications and appropriate architectural solutions
Specification Architecture
Low power and area consumption Second or third order 1-bit modulator with COI digital filter
Possible lowest delay COI digital filter
Lowest number of cycles Optimized filter with new algorithm
Suppression of periodic noise Digital sinc-filter
Wide-range suppression of line frequency
Optimized sinc-filter
Suppression both 50-60Hz simultaneously
Optimized sinc-filter
Uniform output quantization error Modulator & same-order COI filter
sinc filter → rotated sinc filter
rotated sinc filter
rotated sinc filter
• From left to right D=32,64,128 bottom D=128
Design deference between Σ-Δ filter and incremental Σ-Δ
filter Σ-Δ filter incremental Σ-Δ filter
architecture 3-Integreted-filter 1 filter
delay High Low
Number of cycles High Low(key design point)
Suppression of high frequency
Yes(key design point)
No
Uniform output quantization error
No Yes
Power and area consumption
High low
application Continuous application
Discrete application
Work frequency 100Hz-1MHz DC-100Hz
No filters can live without modulatorsThanks for the modulator designers
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