Post on 08-Jul-2018
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Design of VLSI
Circuits and Systems
Prof. Dejan Markovićee216a@gmail.com
UCLA Electrical Engineering
Fall 2015: EEM216A
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D. Markovic / Slide 2
Teaching Staff, Office Hours
Office hours
• Mon & Fri 11am-12:30pm• MSOL: Tue 10-11am
• 56-147E Eng-IV Bldg.
Office hours• Thu 10am-12pm
• CAD tools, labs,
project
1.2
Prof. DejanMarković
Vahagn
Hokhikyan
Office hours
• Wed 5-6pm
• MSOL discussions
MSOL: Yuta
Toriyama
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D. Markovic / Slide 3
Elevator Pitch
Modeling and design
of energy-delay optimal
VLSI circuits and systems
SW=22
SVth=22
SVdd
=16
SW=1
SVth=1
SVdd
=1
SW
SVth=0.2
SVdd=1.5
D/Dref
E / E
r e f
0 0.5 1 1.5
1.5
1
0.5
0
65%
ref
1.3
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D. Markovic / Slide 4
Background
Familiarity with
• Digital ICs
• VLSI design
•CAD tools
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D. Markovic / Slide 5
EE115C vs. EEM216A
• Simple transistor
and circuit models• Circuit design styles
• Logic gate design
•Custom blocks(adders)
• Several transistor
and circuit models• Constrained design
(Power, Area, Speed)
•
RTL, chip synthesis• Test, packaging
115C (intro) 216A (advanced)
circuits circuits + systems
1.5
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D. Markovic / Slide 6
EEM216A Goals (1/2)
Understanding the basic building blocks of VLSI• Transistors/Wires
• Logic Gates and Layout
• Datapath Blocks
Be able to conceptually model a system
• Logic Optimization
• State Machine Design (RTL)
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EEM216A Goals (2/2)
Be able to build a system (using a subset of the tools)• Verilog Modeling
• Synthesis, Place and Route
Understanding the constraints and tradeoffs
• Delay analysis (gates and interconnects)
• Clocking methodology
• System integration issues(Power/Ground routing, Noise)
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Course Objective and Key Outcomes
Energy-performance optimal design:
• Outcome 1: energy and delay models
• Outcome 2: circuit energy-delay optimization
• Outcome 3: high-level description, chip synthesis
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VLSI Design Challenges
• Power-limited performance
• Limited technology improvements
• Methods for energy efficient design
• Flexibility (multi-mode, multi-standard)
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Course Outcomes
1.10
1. CMOS scaling
2. RC transistor model
3. Static CMOS logic gate design
4. Design with HDL (Verilog)
5. Dynamic and leakage power model6. Power and delay calculation
7. Logical effort and gate sizing
8. Energy-delay tradeoff analysis9. Clocking methodologies and timing analysis
10. Design automation using logic synthesis
11. State machine design (ASM or FSM)
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Online Resources
Three places to bookmark:
• EEWeb Grades
• Piazza Q&A
• Wiki Course material
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Everything on the Wiki, Grades on EEWeb
classwiki Lecture notes, homeworks,
tutorials, project, references grades
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icslwebs.ee.ucla.edu/dejan/classwiki
ee216a_studentbruin2015
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ee216a@gmail.com
• Submission of assignments
•Personal queries▪ Before you email, think of WHY can’t
you post the question on Piazza
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Course Material
• Lecture notes
• Homeworks
• CAD tutorials
• Class project
• Selected papers from IEEExplore
(http://ieeexplore.ieee.org)
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Books (Optional)
EE115C textbook• J. Rabaey, A. Chandrakasan, B. Nikolić,
Digital Integrated Circuits: A Design Perspective,
(2nd Edition), Prentice Hall, 2003.
Another popular VLSI textbook
• N. Weste, D. Harris, CMOS VLSI Design:
A Circuits and Systems Perspective, (3rd Edition),
Addison Wesley, 2004.
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Journals and Conferences
Circuits
• IEEE Journal of Solid-State Circuits (JSSC)• IEEE International Solid-State Circuits Conference (ISSCC)
• European Solid-State Circuits Conference (ESSCIRC)
• Symposium on VLSI Circuits (VLSI)
• Custom Integrated Circuits Conference (CICC)
• Other conferences and journals
CAD
• IEEE Transactions on Computer-Aided Design (TCAD)
• International Conference on Computer Aided Design (ICCAD)
• Design Automation Conference (DAC)
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Schedule and Syllabus
1.18
Intro, Scaling
MOS, Delay Models
Logic Design
Logical Effort
Adders
Verilog 1
Latches and FFsVerilog 2
Clocking Methods
Timing Analysis
Logic Synthesis
Midterm
Dynamic Power
Leakage Power
E-D OptimizationMulti-VDD and Clk
Physical Synthesis
No lecture – projects
Thanksgiving holiday
Packaging and Test
FPGA vs. ASIC
Final
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Grading Policy & Organization
• 5 homeworks
• 3 CAD labs
• Project
• Miderm
• Final
15%
6%
30%
24%
25%
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D. Markovic / Slide 20
Gantt Chart
1.20
Hw #1Hw #2
Hw #3
Hw #4
Hw #5
Lab #1
Lab #2
Lab #3Project
Midterm
Final Exam
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D. Markovic / Slide 21
Homework Topics
• Scaling, Models, Logical Effort
• Logic Design, Verilog ALU
• FFs, Verilog FSM
• Clk, Timing Analysis
• Power, E-D Optimization
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D. Markovic / Slide 22
CAD Labs
• Verilog testbench
•PrimeTime, PrimePower
• UPF (Multi-VDD and Clk)
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D. Markovic / Slide 23
Class Project
• Team project (2 partners)
▪ Start teaming up
• Topic TBD
▪ Details in Week 4
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D. Markovic / Slide 24
Generic Technologies
45nm PDKs + library• PDK: Cadence 45nm GPDK
• PDK + lib: Nangate open cell library
(NCSU FreePDK, ASU PTM)
32/28nm EDK + libraries
• EDK + libs: Synopsys kit and libs
▪ Std cell, I/O, mem, PLL, ref. designs
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D. Markovic / Slide 25
CAD Tools
• (HSPICE)
• Logic synthesis
• Physical synthesis
• Circuit simulation
• Logic synthesis
• Physical synthesis
• DRC and LVS
Cadence Synopsys
Mentor
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D. Markovic / Slide 26Physical
StructuralBehavioral
Processor
Hardware Modules
ALUs, Registers
Gates, FFsTransistors
Systems
Algorithms
Register Transfer Logic
Transfer Functions
Rectangles
Cell, Module Plans
Floor Plans
Clusters
Physical Partitions
Design Description: Gajski-Kuhn Y Chart
Synthesis
Physical
DesignVerification
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D. Markovic / Slide 27
Design Styles
Development TimePerformance
E a s e o f d e s i g n
FPGA
Gate
ArrayCell-
based
Fully
Custom
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D. Markovic / Slide 28
Design Styles
Custom Cell-based Array FPGA
• PnR simplified: rows
separated by horiz.
routing channels
• Wiring space notpre-assigned, cell
size can vary
• Fab more complex
than gate array
• Manual PnR: small
or regular designs
• Wiring space pre-
assigned
• Long design cycle• Mask or field prog.
gate array
• Inter cell wiring
using layout sw
• Quick to fabricate
• Array of cells
• Personalization
▪ Soft: mem (Xilinx)
▪ Hard: a-fuse (Actel)
• Immediate spin
• Prototyping
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l
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D. Markovic / Slide 29
Design Styles: Comparison
Style FPGA Gate array Std-cell Full custom
Cell size Fixed FixedFixed
heightVariable
Cell type Prog. Fixed Variable Variable
Cell
placementFixed Fixed In row Variable
Interconnect Prog. Variable Variable Variable
Design time Very fast Fast Medium Slow
Could use a mix of styles
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i h d l
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D. Markovic / Slide 30
Design Methodology
F=AB+C
TOP-DOWN
Architecture
CAD
HDL
IC Design
To design complex circuits in a simple way,
simple components in a complex way need to be analyzed
BOTTOM-UPA B C
74001
2
3
4
5
6
7
14
13
12
11
10
9
8GND
VCC
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Introduction,CMOS Scaling
Prof Dejan Marković
ee216a@gmail.com
EEM216AFall 2015
Th Fi Di i l El i C
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D. Markovic / Slide 32
The First Digital Electronic Computer
Zuse Z3(1941)
1.32
Device: Electromechanical relay
Binary
5 – 10 Hz22b words
2Krelays
Google images
Fi Y L
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D. Markovic / Slide 33
Five Years Later
1.33
ENIAC(1946)
Device: Vacuum tube
Decimal
5M jointshand-soldered
18Ktubes
$500K$6M today
150kW
Google images
Th Fi t PC
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D. Markovic / Slide 34
The First PC
1.34
Simon(1950)
Device: Electromechanical relay
4 ops:
+, −x, >, S2b Reg/ALU
$600Google images
Wh t i th M hi ’ F t ?
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D. Markovic / Slide 35
What is the Machine’s Future?
Mr. Berkeley's answer:
"Simon has two futures. In first place Simon can grow .
With another chassis and some wiring and engineering, the
machine will be able to compute decimally. Perhaps in six
months more, we may be able to have it working on real problems. In the second place, Simon may start a fad of
building baby mechanical brains , similar to the hobby of
building crystal radio sets that swept the country in the
1920's."
1.35
[1956 Berkeley Enterprises Report]
S (Th El t i R b t S i l)
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D. Markovic / Slide 36
Squee (The Electronic Robot Squirrel)
Eye
1.36
[1956 Berkeley Enterprises Report]Hand
Google images
I t t d El t i
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D. Markovic / Slide 37
Integrated Electronics
1.37
1948 (Bell Labs)
1958 (TI)
1971 (Intel)
60kHz
BJT
IC
μP
4004
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D. Markovic / Slide 38
1965
1.38
M ’ L
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D. Markovic / Slide 39
Moore’s Law
• In 1965, Gordon Moore noted that the number of
transistors on a chip doubled every 18 to 24 months
[G. Moore, Electronics, 1965]
“The complexity for minimum component costs has
increased at a rate of roughly a factor of two per year.
Certainly over the short term, this rate can be expected tocontinue, if not to increase. Over the longer term, the
rate of increase is a bit more uncertain, although there is
no reason to believe it will not remain nearly constant for
at least 10 years. That means by 1975, the number ofcomponents per integrated circuit for minimum cost will
be 65,000.”
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D. Markovic / Slide 40
2005
1.40
Transistors / cm2
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D. Markovic / Slide 41
Transistors / cm2
2,000,000ximprovement
1.41
4B
100M
2M
50K
2K
10μm
19725μm
19821μm
1992130nm
200220nm
2012
40 years
Courtesy: Broadcom
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D. Markovic / Slide 42
Size: W, L, tox
Voltage: VDD, VT
1.42
Dennard’s Classical MOSFET Scaling (1974)
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D. Markovic / Slide 43
Dennard’s Classical MOSFET Scaling (1974)
1.43
1/κ
κ
1/κ1/κ
1/κ
1/κ
1/κ2
1
: Device dimension tox, L, W
: Doping concentration Na
: Voltage V: Current I
: Capacitance εA/tox: Delay time/circuit VC/I
: Power dissipation/circuit VI: Power density VI/A
ScalingFactor Device or Circuit Parameter
R. Dennard, JSSC, Oct 1974.
Constant E field Scaling
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D. Markovic / Slide 44
Constant E-field Scaling
Voltage and size scale by the same factor, S (S > 1)• E = V/L = constant
Outcomes:
• More transistors/area 1/S2
• Faster delay 1/S
• Lower energy/op 1/S3
Problem: VT scaling (exponential leakage)
1.44
Constant E field Scaling
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D. Markovic / Slide 45
Constant E-field Scaling
Ended at the 130nm node
1.45
Historical Scaling Trends
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D. Markovic / Slide 46
Historical Scaling Trends
Pentium Pro
Pentium ® 486
3862868086
8085
80808008
40040.1
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
F r e
q u e n c y ( M
H z )
Courtesy:
S. Borkar(Intel)
Pentium 4
Const VDD Const E General
1.46
Power
density
Leakage
power
Technology Scaling is Power Driven
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D. Markovic / Slide 47
Technology Scaling is Power Driven
1.47
Bipolar NMOS CMOS ???
powerwall
powerwall
powerwall
1970 1985 2000
• CMOS delivered better cost performance
▪ It was more energy efficient
▪ It improved the integration level
Bipolar Power Wall CMOS
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D. Markovic / Slide 48
Bipolar Power Wall CMOS
• Technologies: bipolar, nMOS, CMOS
• Constant voltage scaling: increasing power
1.48
Courtesy: Roger Schmidt (IBM)
M o d u l e H e a t F l u x ( W / c m 2 )
Scaling Scenarios: Fixed V Fixed E General
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D. Markovic / Slide 49
Scaling Scenarios: Fixed V, Fixed E, General
Parameter Relation Fixed V Fixed E General
W, L, t ox 1/S 1/S 1/S
V DD, V T 1 1/S 1/U
Area/Device WL 1/S2 1/S2 1/S2
Cox 1/tox S S S
Cgate Cox WL 1/S 1/S 1/Skn, kp Cox W/L S S S
Isat Cox WV 1 1/S 1/U
Current Density Isat / Area S2 S S2/U
Ron V / Isat 1 1 1Intr. Delay Ron Cgate 1/S 1/S 1/S
Power Isat V 1 1/S2 1/U2
P Density Power/Area S2 1 S2/U2
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General Scaling
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D. Markovic / Slide 50
General Scaling
Size scaling S > Voltage scaling U
Voltage scaling slowing down
• VT determined by leakage
• tox also set by leakage
Current increasing by stressing silicon
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Strained Silicon (90nm)
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D. Markovic / Slide 51
Strained Silicon (90nm)
• Increase current to make up the loss due to U < S
1.51
Courtesy: Intel
High-K Metal-Gate (45nm)
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D. Markovic / Slide 52
High-K Metal-Gate (45nm)
• Restored tox scaling at
the 45nm node
1.52
Courtesy: Intel
45nm Interconnects
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D. Markovic / Slide 53
45nm Interconnects
Global wires,
low-R power grid
1.53
Courtesy: Intel
Local interconnects(max density)
45nm Interconnects
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D. Markovic / Slide 54
45nm Interconnects
• M9: very-low-R power routing
1.54
Courtesy: Intel
Changing Layout Styles
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D. Markovic / Slide 55
Changing Layout Styles
65nm layout
1.55
Courtesy: Intel
32nm layout
Challenges in Scaling
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D. Markovic / Slide 56
Challenges in Scaling
Fixed E (Past)
• Scaling reduced cost• Scaling increased
performance
• Performance constrained
• Active power dominates
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General (Now)
• Scaling reduces cost• Materials increase
performance
• Power constrained
• Standby power dominates
130
90
6545
32
Courtesy: Intel
Semiconductor Scaling
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D. Markovic / Slide 57
Semiconductor Scaling
• Integration density continues to grow
• RC delay did not scale
▪ RC delay started to overtake gate delay
• VT did not scale
▪ To cope with leakage
•VDD did not scale▪ To sustain performance growth
1.57
The Limits
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D. Markovic / Slide 58
The Limits
•
System
• Circuit
• Device
• Material
• Fundamental
[J. Meindl, Proc. IEEE, 1995]
1.58
Theoretical
(Physics)
Practical
(Physical +
manufacturing cost)
Circuit Limits
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D. Markovic / Slide 59
Circuit Limits
• Logic levels (gain)
• Energy/transition
• Delay
• Global interconnect
1.59
Logic Levels (Gain)
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D. Markovic / Slide 60
Logic Levels (Gain)
• Distinguish logic 0’s from 1’s
• Restore logic levels |Gain| >1
1.60
≥
2
1 +
l n 2 +
≥
≈ 0.1
≈ 4
(T = 300K)
[J. Meindl, Proc. IEEE, 1995]
Circuit Limits (Cont.)
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D. Markovic / Slide 61
Circuit Limits (Cont.)
• Energy/transition
▪ Neglecting Estatic
• Delay
▪ Limited by IDSat
• Global interconnect▪ Interconnect delay
should not exceed
gate delay1.61
=1
2
∝ ( − )
=1
2
∝ 2.3 +
< 2.3
Practical Limits: Minimum Feature Size
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D. Markovic / Slide 62
Practical Limits: Minimum Feature Size
~130nm is the most
cost-effective
technology
(the last generation
for which deep UV
microlithography
will suffice)
1.62
[J. Meindl, Proc. IEEE, 1995]
Practical Limits: Die Size
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D. Markovic / Slide 63
Practical Limits: Die Size
1.63
[J. Meindl, Proc. IEEE, 1995]
25 mm
8” wafer
40 mm
12” wafer
50 mm
16” wafer
Practical Limits: Packing Efficiency
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D. Markovic / Slide 64
Practical Limits: Packing Efficiency
Packing efficiency = # transistors / min feature area
Layoutdensity
1.64
3Dintegration
[J. Meindl, Proc. IEEE, 1995]
Approaching Atomic Limits
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D. Markovic / Slide 65
pp oac g to c ts
Si atom
0.25nm
1.65
1x
80x
200,000x
20nm FET
Hair
We Have Reached the 130W Power Limit
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D. Markovic / Slide 661.66
N.B. Asadi, PhD Thesis, Stanford 2010.
Moore’s Law and the Long Term
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D. Markovic / Slide 67
g
1965
Whatlevel?
2005
1.67
Moore’s Law and the Long Term
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D. Markovic / Slide 68
g
When?
Within yourworking life?
1965
Whatlevel?
2005
1.68
Scaling Toward 10nm Node
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D. Markovic / Slide 69
g
• Technology: alternative structures andmaterials, post-silicon devices
• Design: billion transistors, GHz operation
22nm
45nm
65nm
32nm
16nm12nm
Bulk/SOI CMOS Multi-gate CMOS Post-Silicon
5 m5 m
5 nm
Source:K. Cao(ASU)
1.69
CMOS Replacement?
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D. Markovic / Slide 70
p
• Replacing CMOS by another more energy efficient
technology is a distant prospect now
• Low-power high-speed CMOS technology is becomingan indispensable, rather than desirable, technology
• Power is the main challenge we need to address
1.70
Wiki / References
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/
Review
EE115CLectures 2-5
(2) MOS IV Model
(3) MOS RC Model(4) Inverter VTC
(5) Propagation Delay
Before next lecture: