Post on 13-Jul-2020
Exercises on Pipeline Hazards
CDA3101 – Spring 2013
Chapter 4 — The Processor —2
Hazards• Due to overlap (pipeline) of inst. execution• Situations that prevent starting the next instruction in the next cycle
• Structure hazards– A required resource is busy
• Data hazard– Need to wait for previous instruction to complete its data read/write
• Control hazard– Deciding on control action depends on previous instruction
Chapter 4 — The Processor —3
Structure Hazards• Conflict for use of a resource• In MIPS pipeline with a single memory
– Load/store requires data access– Instruction fetch would have to stall for that cycle
• Would cause a pipeline “bubble”
• Hence, pipelined datapaths require separate instruction/data memories– Or separate instruction/data caches
• Same for read/write register file?
Chapter 4 — The Processor —4
Data Hazards• An instruction depends on completion of data access by a previous instruction– add $s0, $t0, $t1sub $t2, $s0, $t3
(5‐stage pipeline notation)
Chapter 4 — The Processor —5
Control Hazards
• Branch determines flow of control– Fetching next instruction depends on branch outcome
– Pipeline can’t always fetch correct instruction• Still working on ID stage of branch
• In MIPS pipeline– Need to compare registers and compute target early in the pipeline
– Add hardware to do it in ID stage
Chapter 4 — The Processor —6
Data Hazards in ALU Instructions
• Consider this sequence:sub $2, $1,$3and $12,$2,$5or $13,$6,$2add $14,$2,$2sw $15,100($2)
• We can resolve hazards with forwarding– How do we detect when to forward?– Need to generate proper control signals
§4.7 Data Hazards: Forwarding vs. Stalling
Chapter 4 — The Processor —7
Dependencies & Forwarding
Satisfy through register file
Chapter 4 — The Processor —8
Handling Branch Hazard Delay branch
Scheduling (instruction) slot follow branch is defined as a *delay* slot
Fill delay slot with useful instruction regardless branch outcome, i.e. always execute inst. in the delay slot
Use dynamic branch prediction Branch prediction buffer (aka branch history table) Indexed by recent branch instruction addresses
Chapter 4 — The Processor —9
FIGURE 4.64 Scheduling the branch delay slot with useful inst.Delay Branches
Chapter 4 — The Processor —10
Dynamic Branch Prediction
• In deeper and superscalar pipelines, branch penalty is more significant
• Use dynamic prediction– Branch prediction buffer (aka branch history table)– Indexed by recent branch instruction addresses– Stores outcome (taken/not taken)– To execute a branch
• Check table, expect the same outcome• Start fetching from fall‐through or target• If wrong, flush pipeline and flip prediction
Chapter 4 — The Processor —11
1‐Bit Predictor: Shortcoming• Predict the outcome based on previous outcome• Inner loop branches mispredicted twice!
outer: ……
inner: ……beq …, …, inner…beq …, …, outer
Mispredict as taken on last iteration of inner loop Then mispredict as not taken on first iteration of inner loop next time around
Chapter 4 — The Processor —12
2‐Bit Predictor (per branch)• Only change prediction on two successive mispredictions– One misprediction for nested loop
• Consider the following sequence of actual outcomes for a single static branch. T means the branch is taken. N means the branch is not taken. For this question, assume that this is the only branch in the program.
• T T T N T N T T T N T N T T T N T N• Assume that we try to predict this sequence with a BHT using one‐bit counters. The counters in the BHT are initialized to the N state. Which of the branches in this sequence would be mis‐predicted?
Exercise 1: One‐bit Branch Predictor
• T T T N T N T T T N T N T T T N T N• Assume that we try to predict this sequence with a BHT using one‐bit counters. The counters in the
BHT are initialized to the N state. Which of the branches in this sequence would be mis‐predicted? • You may use this table for your answer:
Exercise 1: One‐bit Branch Predictor
• T T T N T N T T T N T N T T T N T N• Assume that we try to predict this sequence with a BHT using one‐bit counters. The counters in the
BHT are initialized to the N state. Which of the branches in this sequence would be mis‐predicted? • You may use this table for your answer:
Exercise 1: One‐bit Branch Predictor
Exercise 2: Dependence detection• This question covers your understanding of dependences between
instructions. Using the code below, list all of the dependence types (RAW, WAR, WAW). List the dependences in the respective table (example INST‐X to INST‐Y) by writing in the instruction numbers involved with the dependence.
• I0: A = B + C;• I1: C = A ‐ B;• I2: D = A + C;• I3: A = B * C * D;• I4: C = F / D;• I5: F = A ˆ G;• I6: G = F + D;
Exercise 2: Dependence detection• This question covers your understanding of dependences between
instructions. Using the code below, list all of the dependence types (RAW, WAR, WAW). List the dependences in the respective table (example INST‐X to INST‐Y) by writing in the instruction numbers involved with the dependence.
• I0: A = B + C;• I1: C = A ‐ B;• I2: D = A + C;• I3: A = B * C * D;• I4: C = F / D;• I5: F = A ˆ G;• I6: G = F + D;