Ethernet for Control Automation Technology …hzhang/courses/8260/Lectures/Chapter 18...Ethernet for...

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Transcript of Ethernet for Control Automation Technology …hzhang/courses/8260/Lectures/Chapter 18...Ethernet for...

Ethernet for Control Automation Technology (EtherCAT)

Pengfei Renpengfei@wayne.edu

Outline Introduction

Physical Layer

Data Link Layer

Distributed Clocks

Application Layer

EtherCAT Master Characteristics

Outline Introduction

Physical Layer

Data Link Layer

Distributed Clocks

Application Layer

EtherCAT Master Characteristics

Introduction Motivation

The adoption of Ethernet in automation applications: short cycle times and low communication jitters are required.

Standardization EtherCAT Technology Group (ETG): IEC 61158 and

IEC61784

Characteristics Master/Slave Architecture Ring Topology: daisy chain Extensibility

Introduction Each slave device equipped with EtherCAT Slave

Controllers (ESCs) Frame processing and relaying are carried out in hardware

at the same time.

Outline Introduction

Physical Layer

Data Link Layer

Distributed Clocks

Application Layer

EtherCAT Master Characteristics

Physical Layer Communication Support

Two types of physical layers: Ethernet and EBUS Ethernet transceivers interfacing ESCs should: provide either

a standard media-independent-interface (MII) or a reduced one (RMII); support the MII management interface, auto-negotiation, and auto-crossover.

EBUS: only used as a backplane bus and to interconnect modules

Ethernet & EBUS: same sequence of logical bits interoperation

Network Topology Daisy chain wiring + Full-duplex Ethernet Ring 2^16 nodes for each segment

Physical Layer Device Architecture

EtherCAT masters (EMs): standard hardware (Ethernet network interface controller) and dedicated software.

EtherCAT slaves: purposely designed EtherCAT Slave Components (ESCs)

ESCs port: auto-forwarder and loopback

Processing path

Forwarding path

Outline Introduction

Physical Layer

Data Link Layer

Distributed Clocks

Application Layer

EtherCAT Master Characteristics

Data Link Layer Goal

Achieve maximum Ethernet bandwidth utilization and high communication efficiency

Frame Format EtherCAT datagram: Data Link Protocol Data Units (DLPDU)

Data Link Layer DLPDU Format

Data Link Service Data Unit (DLSDU) Working Counter (WKC): check if a command has been

successfully executed by the relevant slaves

Data Link Layer Datagram Header

Data Link Layer Addressing

Physical Addressing: address position (ADP) + address offset (ADO)

o Position (auto-increment ADP) addressing: used only during the start-up and to detect new slaves (- segment topology change)

o Configured (node) addressing: (+ segment topology change)o Broadcast: ADP field is checked but not checked. It is generally

used to initialize slaves. Logical Addressing: ADR bit oriented addressing

o Goal: bandwidth efficiencyo Requirement: fieldbus memory management units (FMMUs)

translating a logical address to a physical address

Data Link Layer Logical Addressing

Data Link Layer Commands

EtherCAT commands are obtained by combining an access type and an addressing mode.

Data Link Layer SyncManager

Problem: concurrent accesses from EM (EtherCAT master) and local application to ESC memory

Solution: SyncManager implemented in hardware Mechanism:

o the buffer must be accessed beginning with the start addresso once access to the start location is granted, the whole buffer

can be accessedo accessing the last location concludes the whole operation

Communication modes:o buffered (3-buffer) mode: EM and local applications always

access the buffer 0 and old data may be discardedo mailbox mode: alternative reading and writing + mailbox lock

Outline Introduction

Physical Layer

Data Link Layer

Distributed Clocks

Application Layer

EtherCAT Master Characteristics

Distributed Clocks Main Features

DC implementation is not mandatory DC relies on specific features of EtherCAT

Terms System time Reference clock: provide system time Local clock Master clock Propagation delay Offset: local clock – reference clock Drift

Distributed Clocks DC Mechanism

Propagation delay measurement: the master sends a synchronization DLPDU, collects all timestamps and compute the propagation delay.

Offset compensation: the master computes the offset between the reference and local clocks for each DC-enabled slave.

Drift compensation: the drift of local clock is corrected through a time control loop (TCL)

External Synchronization Synchronize to an external time source

Outline Introduction

Physical Layer

Data Link Layer

Distributed Clocks

Application Layer

EtherCAT Master Characteristics

Application Layer EtherCAT slave states

Init: initialize the SyncManager channels for mailbox communications

Preoperational: enable mailbox(-mode) communications and initialize the SyncManager channels for process data

Safe operational: mailbox and process data communications are enabled, but the slave outputs are kept in a safe state

Operational: mailbox and process data communications are completely enabled

Bootstrap (operational): download the device firmware

Application Protocols Support multiprotocol higher-level communications using

standardized mailboxes

Application Layer EtherCAT slave states

Outline Introduction

Physical Layer

Data Link Layer

Distributed Clocks

Application Layer

EtherCAT Master Characteristics

EtherCAT Master Characteristics Control Loop

The control loop is a cyclic task with its own predefined period, which, independent of its complexity, has to read and write data from/to the slaves according to the control algorithm.

A distinguishing feature of EtherCAT is its ability to enable very short cycle times.

EtherCAT Master Characteristics Control Loop

EtherCAT Master Characteristics Commercial versus Open-Source Implementations

FPGA based hardware prototype implementation Software implementation: commercial and open-source

o TwinCAT, NI EM, and KPA EMo EtherLab and Simple Open EtherCAT Master (SOME)

EtherCAT Master Characteristics Programming Languages

o Instruction list (IL)o Structured text (ST)o Ladder disgram (LD)o Function block diagram (FBD)o Sequential function chart (SFC)o Other languages (e.g. C)

Outline Introduction

Physical Layer

Data Link Layer

Distributed Clocks

Application Layer

EtherCAT Master Characteristics

Q&A