Post on 24-Aug-2021
ENGR 303 – Introduction to Logic Design Lecture 20
Dr. Chuck BrownEngineering and Computer Information Science
Folsom Lake College
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• Computer microarchitecture overview
• Single Cycle Computer
• Arithmetic Logic Unit (ALU)
Outline for Todays Lecture
ENGR 303
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Microarchitecture
• Computer architecture consists of a high level description of the hardware and instructions
• Instruction set architecture (ISA) is the collection of instructions that specifies the operations of the hardware
• For this course we will study a Single Cycle Computer1 which represents the basic microarchitecture and ISA of a computer CPU
1 Logic and Computer Design Fundamentals, Fifth Edition-2015, Chapter 8, pgs433- 466, by Morris Mano, Charles Kime, and Tom Martin
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Single Cycle Computer
• A Single Cycle Computer , as its name implies, completes an instruction cycle in one clock cycle
• An instruction cycle is the process by which a computer retrieves (fetch) a program instruction from memory, determines the actions (decode) to be taken, and carriers out the actions (execute)
fetch -> decode -> execute
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Block Diagram for Single-Cycle Computer
Figure 8-15, Mano1
A set of registers
Arithmetic Logic Unit memory
Address and data buses
Control interface
Program counter
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Data & Control Paths
• A Single Cycle Computer architecture is divided into a data and control paths
• The datapath has three components– Set of registers
– Microoperations performed on the data stored in the registers, and
– Control interface
• The control path provides the signals that control operations performance in the datapath …based on the program instructions
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Datapath
• The datapath employs a set of registers that hold data with a Arithmetic Logic Unit (ALU) that performs operations on the data
• Basic operations include add, subtract, increment, transfer…as well as logic functions
• The results of the operation are stored back into a destination register
• In the Single Cycle Computer the data transfer from the source register, through the ALU, to the destination register is done in one clock cycle
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Block Diagram of Datapath
Figure 8-1, Mano1
Register File (Four n-bit registers)
Function Unit (ALU & Shifter)
A – address busB – data busC – carry flagD – result busF – external dataG – operationH – shifted dataN – negative flagV – overflow flagZ – zero flag
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Example R1 <- R2+ R3
1. A select, to place contents of R2 onto A bus
2. B select, to place contents of R3 input MUX
B and then onto B bus
3. G select, to declare the arithmetic operation
A + B
4. MF select, place ALU output on MUX F out
5. MD select, to place MUX F out onto D bus
6. Destination select, to select R1
7. Load enable, enable R1 to load the result
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Arithmetic Logic Unit (ALU)
• The ALU is a combinatorial adder circuit that performs basic arithmetic operations on A & B
• A number of selection lines (S0, S1) determine the operation
Figure 8-3, Table 8-1, Mano1
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ALU Design
Table 8-1, Figure 8-4 Mano1
Yi = BiS0 + BiS1
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ALU Arithmetic Circuit
Yi = BiS0 + BiS1
Figure 8-5 Mano1
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ALU Logic Circuit
• Logic to support bitwise operations; AND, OR, XOR, NOT
Figure 8-6 Mano1
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One Stage of ALU
Figure 8-7 Mano1
Figure 8-6
Figure 8-5
S2 = 0 -> arithmetic operation
S2 = 1 -> logic operation
• ALU formed by arithmetic and logic circuits
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ALU Function Select Table
• The resulting function select (FS) operations FS(3:0) = S2 , S1, S0, Cin
Table 8-2, Table 8-1, Mano1
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Lab 10 – ALU Design• Implement the ALU sub-elements of the Function unit• Demonstrate ALU on DE2 board
– Input B: Toggle Switches 15 thru 8– Input A: Toggle Switches 7 thru 0
– Output G: Red LEDs 7 thru 0
– These next 3 are the OpSelect group:– S1: Key Switch 3– S0: Key Switch 2– Cin: Key Switch 1
– Cout: Red LED 17– V: Red LED 16
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The Function Unit
Figure 8-1, Mano1
G Select = FS(3:0) = S2 , S1, S0, Cin
H Select = FS(1:0) = S1, S0
MF Select = S2 & S1
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The Shifter
• The shifter is the second element of the Functional unit and necessary for multiple operations
• A combinational shifter can transfer data from the source register to destination register on one clock
• A combinational shifter can be implemented with multiplexers
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The Shifter Circuit
Figure 8-8, Mano1
H Select
S = 00 -> B passes unchanged
S = 01 -> right shift
S = 10 -> left shift
S = 11 -> don’t care
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Lab 11 – Functional Unit Design
• Implement the basic sub-elements of the function unit
– 8-bit 2 to1 Mux
– ALU Stage
– Shifter
– Zero Detect Module
• Demonstrate Functional Unit on DE2 board
– Shown conditional output bits (V, C, N, Z) for fixed A & B value with a couple FS settings