Post on 21-Jun-2020
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Engineering Design Specification
Arira Design - MX27 Reference Platform
Document #: 800-00355-10SPEC
Revision: 0.5
Date: June 10, 2009
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Revision History
Revision Changes Author/Editor
0.1 Initial authoring BFD
0.2 Review updates BFD
0.3 Block diagram and connectivity updates BFD
0.4 Added IRQ and GPIO mapping, Block diagrams updated ATN
0.5 Battery charging details added, section 7 modified ATN
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Table of Contents
1 Introduction ................................................................................................ 6
1.1 Purpose ........................................................................................... 6
1.2 Scope .............................................................................................. 6
1.3 Reference Documents .................................................................... 6
2 Functional Description ............................................................................... 7
2.1 Functional Block Diagram .............................................................. 7
2.2 MC13783 ......................................................................................... 8
2.3 Memory............................................................................................ 8
2.4 LCD Interface .................................................................................. 9
2.5 USB Interfaces ................................................................................ 9
2.6 I2C Interface .................................................................................. 10
2.7 Expansion board ........................................................................... 11
3 Clock Tree ................................................................................................ 12
4 Reset Control ........................................................................................... 13
5 Power ....................................................................................................... 14
5.1 Power Consumption ..................................................................... 14
6 Board IO ................................................................................................... 18
6.1 Connectors .................................................................................... 18
7 Firmware/Software Dependencies & Component Configuration Settings27
7.1 Hardware Configuration Settings ................................................. 27
8 Manufacturing and Testability ................................................................. 30
8.1 Design for Manufacturing (DFM) .................................................. 30
8.2 Design for Compliance (DFC) ...................................................... 30
8.3 Design for Testability (DFT) .......................................................... 30
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Table of Figures
Figure 1 - Block Diagram .............................................................. 7
Figure 2 - Expansion Board Block Diagram .............................. 11
Figure 3 - Clock Tree .................................................................. 12
Figure 4 - Reset Control .............................................................. 13
Figure 5 – Power Scheme .......................................................... 15
Figure 6 – Battery Charging ........................................................ 17
Figure 7: Micro USB OTG AB Connector .................................. 18
Figure 8: USB Type A Connector ............................................... 19
Figure 9: Microphone ................................................................. 23
Figure 10: Speaker ...................................................................... 23
Figure 11: Stereo Audio Jack ..................................................... 24
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List of Tables
Table 1: Power Consumption ..................................................... 14
Table 2: Micro USB OTG AB Connector Pinout ........................ 18
Table 3: USB Type A Connector Pinout .................................... 19
Table 4: LCD Connector Pinout ................................................. 20
Table 5: Acoustic touch screen Connector Pinout .................... 21
Table 6: Back Gammon Capacitive Touch Screen Connector Pinout 22
Table 7: Stereo Audio Jack Pinout ............................................. 24
Table 8: 3 Pin Serial Port Header Pinout ................................... 24
Table 9: Expansion Connector Pinout ....................................... 26
Table 10: IMX27- Config Strapping ............................................ 27
Table 11: IMX27- GPIO Mapping ............................................... 28
Table 12: ATLAS – Config Strapping ......................................... 28
Table 13: ATLAS - GPIO Mapping ............................................. 29
Table 14: STM32F103 – Config Strapping ................................ 29
Table 15: STM32F103 - GPIO Mapping .................................... 29
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1 Introduction
1.1 Purpose
This document is intended to define the hardware components of the Arira Design MX27 reference platform, and how the components are interconnected. This document is not intended to act as or replace a theory of operations document or marketing requirements document (MRD), rather it is intended to provide detailed insight as to the specific components used on the board, their interconnectivity, and configuration.
1.2 Scope
The intended audience of this document is hardware and firmware/software developers. The contents of this document range from expected power dissipation on the board to addressable contents.
1.3 Reference Documents
MCIMX27 Datasheet Rev 1.2, 07/2008
MCIMX27 Reference manual rev 0.2 & Addendum
MC13783 Power Management and Audio Circuit, User’s Guide, MC13783UG Rev 3.6, 9/2007
MC13783 Technical Data, MC13783/D Rev 3.4, 3/2007
MC13783 Information for GPL Drivers, Reference Manual, MC13783GPLDRM Rev 1.1, 4/2008
External Component Recommendations for the MC13783 Reference Design Application Note, AN3295
MC13783 Buck and Boost Inductor Sizing Application Note, AN3294
Interfacing the MC13783 Power Management IC with i.MX31 Application Note, AN3276
MC13783 Recommended Audio Output SPI Sequences Application Note, AN3261
Voltage Drop Compensation on the MC13783 Switchers Application Note, AN3249
Battery Management for the MC13783 Application Note, AN3155
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2 Functional Description
The following sections are intended to provide basic functionality and interconnects used in areas critical to the hardware development of the Arira Design MX27 Reference Platform hardware design.
2.1 Functional Block Diagram
3.5mmSTEREO JACK
MC13783
CAPACITIVETOUCHCONN
ADC
ADDR:b1010000;0X50
ADDR:b0011100;0X1D
KEYPAD
JTAG
UART 3
I2C2
FEC
CSI
UART 2
EXPA
NSI
ON
CO
NN
APR TOUCHSCREENCONNECTOR
SSI4
MICROPHONE (MONO)
256BYTEID PROM
SPEAKER (MONO)
ACCELERO-METER
SSI2
SSI1
LCDC
CSPI1
CSPI3
LCD CONNECTOR
ANALOG LINES
RESISTIVETOUCH CTRL
SD2SD CARD CONN
Li-IonBATTERY
ADDR:b1000100;0X44 SPI
MCUSTM32F103CB
I2CLIGHT SENSOR
NANDFLASH
DDR SDRAM
i.MX27
MICRO USBOTG CONN
USBCONNTYPE A
USBTRANSCEIVER HIGH SPEED
USB H2
USB OTG
WEIM
ESDRAMC
CPU
32 Bits
UART 1
128M BYTE
64M BYTE
Figure 1 - Block Diagram
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2.2 MC13783
The Freescale MC13783 Atlas chip provides power management, audio interfaces, and user interface components to the MX27 reference platform.
Connectivity to the i.MX27 chip is provided through 3 interfaces. One of two available SPI interfaces is used as the control/status interface to/from the i.MX27, and two SSI interfaces are used for the audio interfaces to/from the i.MX27.
The interface to the outside world is through a mini USB AB connector. The Atlas chip provides on chip Full Speed USB OTG transceiver and functionality to be both a host (OTG A device) or slave (OTG B device).
Power management includes integrated battery charger control, through the USBOTG connector. Current and voltage monitoring of the battery is provided by an on chip ADC.
The Atlas chip includes 5 switching power supplies (4 buck and 1 boost) and 18 linear regulators, which are used to power the MX27. Power sequencing is controlled through strapping options on the chip. This is important as the core voltage of the i.MX27 is required to come on before IO voltages.
The audio interfaces to the i.MX27 are two interchangeable SSI buses, both with master/slave support. One of 3 available audio inputs (MC1RIN) will be used for the mono microphone input. A handset speaker will be driven by the ASP integrated amplifier, and a stereo headphone jack will be driven by the AHS amplifiers.
A touch screen interface provides the circuitry required for a 4-wire resistive touch screen.
2.3 Memory
The Arira Design MX27 Reference Platform will have a single chip of mobile 64 MB of DDR SDRAM, upgradable to 128 MB, 128 MB of NAND Flash, upgradable to 4GB, and a Micro SD card interface.
2.3.1 DDR SDRAM
The DDR SDRAM will be implemented with Micron MT46H16M32LFCM-7:B or similar part. This is a Mobile DDR SDRAM arranged in 4 Banks x 4Mb x 32, for a total of 64 MB. The i.MX27 incorporates a DDR SRAM controller that runs up to 133MHz. The controller supports 64Mb to 2Gb synchronous DRAM devices with 4 banks, and has two independent chip selects if multiple chips are used.
2.3.2 NAND Flash
The Flash will be implemented using a Micron MT29F1G08ABCHC-ET or similar part (100-01597-00). This is a 1.8V IO and core voltage part, 128Mx8 in a 63 ball VFBGA package. The i.MX27 incorporates a NAND Flash controller that supports 8-bit and 16-bit parts, with page sizes of 512 B, 2KB or 4KB.
2.3.3 Micro SD Card Interface
An SD card slot connector will be placed on the Arira Design MX27 Reference Platform. The connector used will be a Yamaichi FPS009-2700-0 or similar part (200-01126-00). The i.MX27 has two dedicated Secure Digital Host Controller interfaces, one of which will be connected on board, the other will go off
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board through the expansion connector. Micro SD cards may be plugged into this connector for memory expansion, etc.
2.4 LCD Interface
The MX27 reference platform will interface to an 4.3” Liquid Crystal Display, with integrated white LED back light, and resistive touch screen.
2.4.1 LCD Data Interface
The i.MX27 chip has an integrated LCD controller. This will interface to an LCD through a 40 pin FPC connector.
2.4.2 LCD Back Light Interface
The back light on the LCD panel will be controlled through an i.MX27 GPIO output. A PWM circuit implemented with a TI TPS61161 (100-01521-00) LED Driver with PWM brightness control.
2.4.3 Touch Screen Interface
The Atlas chip provides the a touch screen interface - the circuitry required for a 4-wire resistive touch screen. A four pin FPC connector is used to connect to the LCD/touch screen assembly.
2.5 USB Interfaces
The i.MX27 chip has 3 available USB interfaces: one “On The Go” High Speed interface, one High Speed Host Interface, and one Full Speed Host interface.
2.5.1 USB OTG Full Speed Interface
The USB OTG interface from the i.MX27 is connected to the Atlas chip. The Atlas chip provides an on board Full Speed USG OTG transceiver. Note that the i.MX27 supports High speed, but the Atlas chip only has a Full speed transceiver.
A mini USB AB connector will be used to connect to the outside world. The ID pin from this connector is used to determine who is to drive the power on the USB OTG interface. The Atlas chip provides on chip USB OTG functionality, and will control power input or output to the connector. When the board is in USB slave mode, the 5V from the host will be used to charge LI battery.
2.5.2 USB Host High Speed Interface (WIFI)
The USB Host HS interface from the i.MX27 will be connected to an NXP ISP1504A (100-01407-00). This tranciever will be used to connect to a HS USB WIFI device – TBD.
2.5.3 USB Host Full Speed Interface
The USB Host FS interface from the i.MX27 is not used on baord.
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2.6 I2C Interface
The I2C interface will have a 3-axis accelerometer, light sensor and a 256 byte IDPROM.
2.6.1 3-axis I2C accelerometer
The accelerometer will be implemented using an STMicro LIS302DL (100-01637-00). This device has two programmable interrupt outputs which can be configured for thresholds and timings.
2.6.2 Light sensor
Intersil ISL29003IROZ is used as light sensor. This device has one interrupt line to CPU besides the I2C interafce
2.6.3 ID PROM
The ID PROM will be implemented using an Atmel AT24C02A 2-wire serial EEPROM (100-01275-00). This device can be used to store manufacturing information such as fab and assembly part numbers and revisions, and board configuration information.
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2.7 Expansion board
Expansion board connector on the Arira Design MX27 Reference Platform board will be an 80 pin .8mm pitch double row connector from Samtec, QSE-040-01-F-D-A (200-00932-00). The mating connector on the Expansion Board will be the Samtec QTE-040-01-F-D-A (200-01194-00). The stack height of these two connectors is 5.0mm.
An expansion board will bring unused interfaces on the i.MX27 chip. For bring up of the reference board, an Ethernet PHY and an RS-232 transceiver are required. Other interfaces will be brought to a header for debug/testing purpose. See Figure 2 - Expansion Board Block Diagram below.
EXPANSIONCONN
UART1
CSI
KEYPAD
UART3
FECMII
MAX3222RS-232Buffer
SMSCLAN8700C
100 milHeader
RJ45With
MagneticsMDI
DB9RS-232-1
I2C
JTAG JTAG CONNECTOR
Figure 2 - Expansion Board Block Diagram
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3 Clock Tree
Figure 3 - Clock Tree
CS
PI3
CLK
PRI
CLK
CSI C
LKS
FEC
CLK
CPU
USB
TRAN
SCEI
VER
HIG
H SP
EED
DD
R SD
RAM
64M
BSD
CLK
133M
Hz
DIF
F
60M
Hz
XTA
L32K
EXTA
L26M
USB
H2_
CLK
STM
32F1
03C
B
EXPA
NSIO
N C
ONN
ECTO
R
8MH
z
XTA
L
32K
Hz
SPI C
LKAD
C
SSI4
CLK
APR
TOUC
H
CO
NN
26M
Hz
OSC
i.MX2
7
MC
1378
3
CSP
I1 C
LK
NO
TIN
STA
LLED
32K
Hz
26M
Hz
0Ohm
LCD
CO
NN
SS
I1 C
LK1.
41M
Hz
LCD
CLK
SS
I2 C
LK
CLK
32 M
CU
AUD
IO1.
41M
Hz
CLK
026
MH
zC
LIA
& B
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4 Reset Control
Power management and reset control is provided by the Atlas chip. See Figure 4 - Reset Control below for a diagram of reset flow.
USB3317 GPIORESET_L
RESET_OUT
i.MX27
MC13783 POWER_ON_RESETRESETSWITCH
RESET_IN
CPU
PORPM_RESET_MCU
PM_RESET
EXPA
NSIO
N C
ONN
ECTO
R
Figure 4 - Reset Control
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5 Power
5.1 Power Consumption
LCDBL VATLAS +2.8V_STBY VIOLO VIOHI VGEN VMMC1 Voltage (V) --> 19.2 2.8 2.8 1.8 2.8 1.5 3
Devices TYP (mA)
MAX (mA)
TYP (mA)
MAX(mA)
TYP(mA)
MAX(mA)
TYP (mA)
MAX (mA)
TYP(mA)
MAX(mA)
TYP (mA)
MAX (mA)
TYP (mA)
MAX (mA)
CPU 10 10 10 10 MC13783 9.5 12 DDR SDRAM FLASH WIFI Module LCD 20 22 7 10 USB HS Transceiver 28 34 IDPROM Light Sensor Accelerometer 0.3 0.4 CAP Touch screen -CPU CAP Touch screen -ADC Resistive touch screen APR touch screen 2 10 Ethernet PHY chip 37.4 41.3 Serial Transceiver Level shifter 0.05 0.05 Micro SD LED x 7 15 30 26MHz Oscillator 10 10
Total 20 22 9.5 12 0.3 0.4 30.05 44.05 10 10 10 10 69.4 91.3 Regulator output power (mW) 384 422 26.6 34 0.84 1.12 54.09 79.29 28 28 15 15 208.2 273.9 Regulator efficiency (%) 85 80 80 80 80 80 80 Regulator input power (mW )(TYP) 451.8 33.3 1.05 67.6125 35 18.75 260.25 Regulator input power (mW)((MAX) 497 43 1.4 99.1125 35 18.75 342.375 VMMC2 VRF2 VRF1 SW1AB SW2A SW2B 5V5 Voltage (V) --> 3 2.8 2.8 1.45 1.8 1.8 5
Devices TYP (mA)
MAX (mA)
TYP (mA)
MAX(mA)
TYP(mA)
MAX(mA)
TYP (mA)
MAX (mA)
TYP(mA)
MAX(mA)
TYP (mA)
MAX (mA)
TYP (mA)
MAX (mA)
CPU 20 20 20 20 300 300 20 30 10 10 MC13783 DDR SDRAM 100 120 FLASH 10 20 WIFI Module 200 200 LCD USB HS Transceiver 3 4 7 10 IDPROM 2 3 Light Sensor 0.29 0.3 Accelerometer CAP Touch screen -CPU 50 50 CAP Touch screen -ADC 0.9 1 Resistive touch screen APR touch screen Ethernet PHY chip 4.1 4.7 Serial Transceiver 0.3 1 Level shifter 0.05 0.1 Micro SD 30 45 LED x 7 10 20 26MHz Oscillator
Total 60.9 71 26.7 29 53 69 300 300 120 150 20 30 207 210 Regulator output power (mW) 182.7 214 74.9 81 148 193 435 435 216 270 36 54 1035 1050 Regulator efficiency (%) 80 80 80 90 90 90 80 Regulator input power (mW )(TYP) 228.4 93.6 186 483.333 240 40 1293.8 Regulator input power (mW)((MAX) 267 102 242 483.333 300 60 1312.5
Table 1: Power Consumption
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5.1.1 Board Power scheme
2.8V
CPU IO
2.8V
2.8V
350mA
LDO - VRF2
1.5V
CPU CLK(OSC26VDD)
CPU PLL
CPU IO
CPU CORE
VBKUP2
DCDC - SW2A500mA
DCDC - SW2B500mA
CPU IO(NVDD13)
PWR IN(MICRO USB CONN)
5VTO USB CONN (WIFI)
BATTERY
CPU RTC(OSC32VDD,RTCVDD)
3.0VLCD MODULEETHERNET PHY
3.3V
PWR IN (DC JACK)
BOOST1A
100mA
19.2VLCD BACK LIGHT
350mA
VMMC1
LDO - TPS76133350mA
VMMC2
3.0V
LDO - VIOHI200mA
LDO - VGEN200mA
LDO - VRF1350mA
DCDC - SWIA500mA
VREG
VREG
CAP TOUCH CIRCUIT
BOOST - SW4350mA
DDR
1.8V
VBKUP1
FLASH
1.8V500mA
DCDC - SW2A
(NVDD7, NVDD11,NVDD12, NVDD14,NVDD15)
(MPLLVDD,UPLLVDD,FPMVDD)
(NVDD1)
(NVDD2,NVDD3,NVDD4)
(QVDD)
(NVDD5, NVDD6,NVDD8, NVDD9,NVDD10, AVDD)
MC13783(On Expansion board)
Figure 5 – Power Scheme
The i.MX27/MX27L processor consists of three major sets for power supply voltage named QVDD (core logic supply), FUSEVDD (analog supply for FUSEBOX), and NVDD VDDA (IO supply). The External Voltage Regulators and power-on devices must provide the applications processor with a specific sequence of power and resets to ensure proper operation. It is important that the applications processor power supplies be powered-up in a certain order to avoid unintentional fuse blown. QVDD should be powered up before FUSEVDD. The recommended order used in Audio puck is: 1. QVDD(1.5 V) 2. FUSEVDD (1.8 V) NVDD (1.8/2.775 V), and Analog Supplies (2.775 V)
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5.1.1 Power ON & Power states
Board can be brought to active RUN mode using the PWR button during development and using the accelerometer afterwards.
Connecting the USB power or attaching a fully charged battery can also turn the board ON
Keeping the power button pressed for >4sec will turn the board OFF.
The board is supposed to stay powered by battery all the time with the following power saving options.
LCD back light turned OFF and CPU in a lower core frequency and reduced core voltage
Putting CPU in Sleep mode is the largest power saving mode. All the power rails will be active in this mode and the system can be waken up by the accelerometer interrupt activating the PON pin of ATLAS chip.
Back up power modes are not supported even though VBKUP1 and VBKUP2 are connected. System is expected to go to an unplanned power-off In case of a battery removal or battery contact bounce.
Make the VMMC1 and VMMC2 = 3.0V by setting VMMC1 [2:0] = VMMC2 [2:0] = 111
Also make SW3 = 5.0V . SW3[1:0] = 00.
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5.1.2 Battery charging
Battery charging module is configured in dual path charging with an additional DC Jack as shown below for faster battery charging and supplying power when the USB OTG port is a host port.
Figure 6 – Battery Charging
M1 & M2 (Q6 and Q17 in the schematics) are Battery charge path regulator, M4 (Q4) is the external input voltage regulator and M3 (Q3) is the battery voltage switch.
Application of a charger can be detected by the CARGDETS, USB4V4S, and SE1S bits. Presence of a DC jack can be detected by the DC_JACK_PRSNT signal connected to CPU GPIO PF16. Board can use more power if DC Jack is present (2.5A from DC jack as opposed to 500mA from USB). Also the battery can be fast charged at 1C rates (1.2A) if DC jack is present.
Power source for charging can be either from the Micro USB OTG connector or the DC Jack. Hardware will enable the power source as DC jack if both USB and DC jack are plugged in.
Turn the charge path regulator (M1 and M2) off by setting ICHRG[3:0] = 0000’b if both the USB and DC jack connector are absent to prevent possible current loops.
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6 Board IO
6.1 Connectors
The following is a list of interfaces into / out of the MX27 reference platform.
• Mini USB connector • USB Type A connector (for external modules like a Wi-Fi module) • LCD connector • Acoustic touch screen connector • Capacitive touch screen connector • Stereo Headphone Jack • Speaker • Microphone • 3 pin Serial Port Header • Expansion Connector •
6.1.1 Micro USB OTG AB Connector
Figure 7: Micro USB OTG AB Connector
Number Function 1 USB OTG Power – In or Out 2 Data - 3 Data + 4 ID 5 Ground
Table 2: Micro USB OTG AB Connector Pinout
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6.1.2 USB Type A Connector
Figure 8: USB Type A Connector
Number Function 1 USB Power Out 2 Data - 3 Data + 4 Ground
Table 3: USB Type A Connector Pinout
6.1.3 LCD connector (LCD with resistive touch panel)
Number Function 1 LCD Back light cathode 2 3 LCD Back light Anode 4 5 GND 6 RESET_L 7 NC 8 TSRIGHT
Resistive touch panel signals 9 TSTOP 10 TSLEFT 11 TSBOTTOM 12 NC 13 NC 14 LCD_BLU0 15 LCD_BLU1 16 LCD_BLU2 17 LCD_BLU3 18 LCD_BLU4 19 LCD_BLU5 20 NC
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Number Function 21 NC 22 LCD_GRN0 23 LCD_GRN1 24 LCD_GRN2 25 LCD_GRN3 26 LCD_GRN4 27 LCD_GRN5 28 NC 29 NC 30 LCD_RED0 31 LCD_RED1 32 LCD_RED2 33 LCD_RED3 34 LCD_RED4 35 LCD_RED5 36 LCD_HSYNC 37 LCD_VSYNC 38 LCD_DCLK 39 NC 40 NC 41 LCD power 42 43 SS0 44 GND 45 NC 46 GND 47 NC 48 NC 49 SCLK 50 MOSI 51 NC 52 DE 53 GND 54 GND
Table 4: LCD Connector Pinout
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6.1.4 Acoustic touch screen Connector (APR)
Number Function 1 GND 2 NC 3 GND 4 NC 5 GND 6 GND 7 GND 8 GND 9 APR_CONN_SCLK 10 APR_CONN_SERO 11 APR_CONN_SERI 12 APR_CONN_SFR 13 NC 14 POWER 15 POWER 16 POWER
Table 5: Acoustic touch screen Connector Pinout
6.1.5 Capacitive touch screen connector (Back Gammon)
Number Function 1 GND 2 AC_SHIELD 3 AC_SHIELD 4 AC_SHIELD 5 AC_SHIELD 6 AC_SHIELD 7 AC_SHIELD 8 AC_SHIELD 9 AC_SHIELD 10 AC_SHIELD 11 AC_SHIELD 12 AC_SHIELD 13 CIN11 14 CIN10 15 CIN11 16 CIN10 17 CIN9 18 CIN10 19 CIN9 20 CIN8 21 CIN9 22 CIN8
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Number Function 23 CIN7 24 CIN8 25 CIN7 26 CIN6 27 CIN7 28 CIN6 29 CIN5 30 CIN6 31 CIN5 32 CIN4 33 CIN5 34 CIN4 35 CIN3 36 CIN4 37 CIN3 38 CIN2 39 CIN3 40 CIN2 41 CIN1 42 CIN2 43 CIN1 44 CIN0 45 CIN1 46 CIN0 47 AC_SHIELD 48 AC_SHIELD 49 GND 50 GND
Table 6: Back Gammon Capacitive Touch Screen Connector Pinout
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6.1.6 Microphone
Figure 9: Microphone
6.1.7 Speaker
Figure 10: Speaker
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6.1.8 Stereo Audio Jack
Figure 11: Stereo Audio Jack
Number Function 1 GND (Sleeve) 2 Left Out (Tip) 3 Right Out (Ring)
Table 7: Stereo Audio Jack Pinout
6.1.9 3 Pin Serial port header
Number Function 1 Receive input 2 GND 3 Transmit Output
Table 8: 3 Pin Serial Port Header Pinout
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6.1.10 Expansion Connector
Number Function 1 +5V5 2 +5V5 3 +5V5 4 +5V5 5 RESET_OUT_L 6 TMS. 7 RTCK 8 TCK 9 TDI 10 NC 11 TRST_B 12 NC 13 TDO 14 NC 15 +2V8-1 16 +2V8-2 17 +2V8-1 18 +2V8-2 19 CPU_GPIO_1 20 CPU_GPIO_2 21 UART1_RTS 22 UART1_CTS 23 UART1_RXD 24 UART1_TXD 25 I2C2_SCL 26 PM_RESETB_MCU 27 I2C2_SDA 28 PM_PON_L 29 UART3_RTS 30 UART3_CTS 31 UART3_RXD 32 UART3_TXD 33 KP_COL5 34 KP_COL4 35 KP_COL3 36 KP_COL2 37 KP_COL1 38 KP_COL0 39 KP_ROW5 40 KP_ROW4 41 KP_ROW3 42 KP_ROW2 43 KP_ROW1 44 KP_ROW0 45 FEC_TXD0
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Number Function 46 FEC_TXD1 47 FEC_TXD2 48 FEC_TXD3 49 FEC_TX_CLK 50 FEC_TX_ER 51 FEC_TX_EN 52 FEC_RXD0 53 FEC_RXD1 54 FEC_RXD2 55 FEC_RXD3 56 FEC_RX_CLK 57 FEC_RX_ER 58 FEC_RX_DV 59 FEC_CRS 60 FEC_COL 61 FEC_MDIO 62 FEC_MDC 63 CSI_HSYNC 64 CSI_VSYNC 65 CSI_PIXCLK 66 CSI_MCLK 67 CSI_D0 68 CSI_D1 69 CSI_D2 70 CSI_D3 71 CSI_D4 72 CSI_D5 73 CSI_D6 74 CSI_D7 75 EXP_BRD_DET_L 76 BARREL_PWR_PRSNT 77 5V Power IN 78 5V Power IN 79 5V Power IN 80 5V Power IN
Table 9: Expansion Connector Pinout
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7 Firmware/Software Dependencies & Component Configuration Settings
7.1 Hardware Configuration Settings
The following sections provide hardware strapping and GPIO assignments on the MX27 reference platform for i.MX27 CPU, ATLAS Companion chip and the STM32F103 MCU
7.1.1 CPU IMX27
7.1.1.1 Configuration Strapping
The following tables list the strapping configuration implemented on the Freescale i.MX27 CPU
Signal Value Output Signals Active Device (Boot Internal)
Output Signals Active Device (Boot External)
Boot Address
Boot [3:0]
0000 iROM (Bootstrap USB/UART) iROM Bootstrap USB/UART 0x00000030 0010* iROM (8-bit 2 Kbyte NAND Flash) 8-bit 2 Kbyte NAND Flash 0xD8000000 0011 iROM (16-bit 2 Kbyte NAND Flash) 16-bit 2 Kbyte NAND Flash 0xD8000000 0100 iROM (16-bit 512 byte NAND Flash) 16-bit 512 Kbyte NAND Flash 0xD8000000 0101 iROM (16-bit CS0 at D[15:0] (NOR Flash)) 16-bit CS0 at D[15:0] (NOR Flash) 0xC0000000 0110 Reserved Reserved 0xC0000000 0111 iROM (8-bit 512 byte NAND Flash) 8-bit 512B NAND Flash 0xD8000000
Table 10: IMX27- Config Strapping
* Default Strapping
The Default strapping needs to be change to 0000 to use the iROM boot, for booting through UART to program the BGA NAND Flash initially. Installing shorting jumper on J33 will put CPU in iROM boot mode.
7.1.1.2 GPIO Mapping
The table below lists signal names assigned to the muxed GPIO pins, and the function of these signals
CPU Pin GPIO Function on
Audio Puck Comment
B3 PA27 CPU_TSTOP Resistive gesture touch screen signals. These signals can be driven by the MC13783 signals LEDG1& LEDR1 (pin E11& B10) or the CPU GPIOs PA26 & PA27. Configure the 2 CPU GPIOs as inputs or High Z outputs when ATLAS chip is used to control the resistive gesture touch screen. Make the ATLAS LEDG1 & LEDR1 low when CPU is controlling the resistive gesture touch screen control lines.
D2 PA26 CPU_TSRIGHT
W18 PF20 EXP_BRD_DET_L Expansion board detect signals. Low = Expansion board present AC19 PF19 PWRFAIL High = Voltage at BP (pin B13 of ATLAS) is below UVDET Y18 PF18 LOBATB High = Voltage at BP (pin B13 of ATLAS) is below LOWBATL
AD19 PF17 PWRRDY To indicate the Switcher outputs are reached their new set value Normally high, goes low when a new voltage is set on DVS, comes back high again once the voltage reaches the new set point.
Y19 RF16 DC_JACK_PRSNT High = DC Jack plugged in to the expansion board AC20 PF14 USB2_RESET_L Reset to the USB PHY chip USB3317. CPU must reset the PHY chip once
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CPU Pin GPIO Function on
Audio Puck Comment
the GPIOs are stable in order for the PHY to sample the CLKOUT pin as an output. (if the CPU GPIOs drives CLKOUT high during power up, then CLKOUT will become an input on the PHY chip)
W19 PF13 CSP3_INT Primary SPI interrupt from MC13783. Active high
AD20 PF12 ACC_INT1 Interrupt from Accelerometer. Accelerometer has two configurable interrupt lines. INT2 must be configured as active low in order for this signal to act as the power ON signal.
W20 PF11 LS_INT Active low Interrupt from light sensor AC21 PF10 CPU_GPIO_1 Used as LCD_RESET signal.
U20 PF9 CPU_GPIO_2 GPIO to expansion board for future use. Terminated on the breakout headers on expansion board
AD21 PF8 LED_RED High = LED ON V20 PF7 LED_GREEN High = LED ON B11 PC31 PWROFF Signal from CPU for power off after a power fail (Not used)
C9 PC30 WDI Watch dog to MC13783. Not used by default. Install R228 and R230 to connect WDI to MC13783. WDI on MC13783 is just pulled high by default. (Not used)
A11 PC29 ST_BOOT0 These signals are used to program the ST chip during every power cycle. Make BOOT0 =1 and pulse ST_RESET_L to program the ST chip through UART2. Make BOOT0= Z and pulse ST_RESET_L to Boot the ST chip in normal mode. Make both signals High Z if not used.
E10 PC28 ST_RESET_L
Table 11: IMX27- GPIO Mapping
7.1.2 Companion chip-ATLAS-MC13783
7.1.2.1 Configuration strapping
Signal Value Output Signals Active Device (Boot Internal) Remarks
CHRGMOD[1:0]
00 RESERVED
Battery charge mode configuration
Z0 DUAL PATH (Default) 10 SEPERATE INPUT DUAL PATH 0Z RESERVED ZZ SINGLE PATH 1Z SEPERATE INPUT SINGLE PATH 01 RESERVED Z1 SERIAL PATH 11 SEPERATE INPUT SERIAL PATH
UMOD[1:0]
00 SE unidirectional 6-wire
USB OTG input to PHY mode configuration 0Z SE bidirectional 4-wire 1X Diff unidirectional 6-wire (Default) 01 Diff bidirectional 4-wire
Table 12: ATLAS – Config Strapping
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7.1.2.2 GPIO Mapping
ATLAS Pin GPIO Function on Audio Puck Comment
G8 GPIO1 No Connect This pin is not used. It’s floating. F6 GPIO1 No Connect This pin is not used. It’s floating. E5 GPIO1 No Connect This pin is not used. It’s floating. G9 GPIO1 No Connect This pin is not used. It’s floating. E11 LEDG1
Driver for resistive gesture touch panel
These pins control the FETs used for resistive gesture touch panel. Make these pins low when CPU GPIOs are used for resistive gesture touch panel control
B10 LEDR1
Table 13: ATLAS - GPIO Mapping
7.1.3 Capacitive touch screen micro controller - STM32F103CB
7.1.3.1 Configuration strapping
Signal Value Output Signals Active Device (Boot Internal) Remarks
BOOT[1:0] X0 MAIN FLASH (DEFAULT)
STM32F103CB boot mode configuration 01 SYSTEM MEMORY
11 EMBEDDED SRAM
Table 14: STM32F103 – Config Strapping
7.1.3.2 GPIO Mapping
MCU Pin GPIO Function on
Audio Puck Comment
43 PB7 ADC_CS_L ADC Chip select . Active low 10 PA0 ADC_INT_L Active low interrupt from ADC
46 PB9 GPIO_PB9 Connected to GPIO pin of ADC Also drives Red LED, 1 = LED ON
41 PB5 GPIO_PB5 Drives GREEN LED, 1 = LED ON
Table 15: STM32F103 - GPIO Mapping
7.1.4 Power supply and board specific settings.
Set VMMC1 & VMMC2 voltages to 3.0V. (Register 31 and Register 33)
Set VSW3 voltage to 5.0V. It defaults to 5.5V (Register 29)
Use CPU GPIO PF10 as LCD reset signal.
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8 Manufacturing and Testability
8.1 Design for Manufacturing (DFM)
Since the board is not necessarily targeted for manufacturing at a particular contract manufacturer, industry standard DFM guidelines will be used.
8.2 Design for Compliance (DFC)
The board will be designed with the following compliance requirements in mind:
• FCC Part 15 (Class B) • UL1950 • TBD
8.3 Design for Testability (DFT)
8.3.1 JTAG
There are 20 pin standard ARM JTAG connectors for the i.MX27 CPU (Connector on expansion board) and the ST micro controller (Connector on Main board)
8.3.2 In Circuit Testing
TBD