Encoders, DeMUXs & MUXs. Outline Encoder Demultiplexer Multiplexer Multiplexer IC Package.

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Transcript of Encoders, DeMUXs & MUXs. Outline Encoder Demultiplexer Multiplexer Multiplexer IC Package.

Encoders, DeMUXs & MUXs

Outline

Encoder

Demultiplexer

Multiplexer

Multiplexer IC Package

Outline

Encoder

Demultiplexer

Multiplexer

Multiplexer IC Package

Encoder (1/5)

Encoding is the converse of decoding.

Given a set of input lines, where one has been selected, provide a code corresponding to that line.

Contains 2n (or fewer) input lines and n output lines.

Implemented with OR gates.

An example:

4-to-2 Encoder

F0

F1

F2

F3

D0

D1

Select via switches 2-bits

code

Encoder (2/5)

Truth table:F0 F1 F2 F3 D1 D01 0 0 0 0 00 1 0 0 0 10 0 1 0 1 00 0 0 1 1 10 0 0 0 X X0 0 1 1 X X0 1 0 1 X X0 1 1 0 X X0 1 1 1 X X1 0 0 1 X X1 0 1 0 X X1 0 1 1 X X1 1 0 0 X X1 1 0 1 X X1 1 1 0 X X1 1 1 1 X X

Encoder (3/5)

With the help of K-map (and don’t care conditions), can obtain:

D0 = F1 + F3

D1 = F2 + F3

which correspond to circuit:

F0

F1

F2

F3D1

D0Simple 4-to-2 encoder

Encoder (4/5)

Example: Octal-to-binary encoder. At any one time, only one input line has a value of 1. Otherwise, need priority encoder (not covered).

Inputs Outputs

D0 D1 D2 D3 D4 D5 D6 D7 x y z

1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1

Encoder (5/5)

Example: Octal-to-binary encoder.

Exercise: Can you design a 2n-to-n encoder without the K-map?

An 8-to-3 encoder

D0

D1

D2

D3

D4

D5

D6

D7

z = D1 + D3 + D5 + D7

y = D2 + D3 + D6 + D7

x = D4 + D5 + D6 + D7

Outline

Encoder

Demultiplexer

Multiplexer

Multiplexer IC Package

Demultiplexer (1/2)

Given an input line and a set of selection lines, the demultiplexer will direct data from input to a selected output line.

An example of a 1-to-4 demultiplexer:

S1 So Y0 Y1 Y2 Y30 0 D 0 0 00 1 0 D 0 01 0 0 0 D 01 1 0 0 0 D

demuxData D

Outputs

select

S1 S0

Y0 = D.S1'.S0'

Y1 = D.S1'.S0

Y2 = D.S1.S0'

Y3 = D.S1.S0

Demultiplexer (2/2)

The demultiplexer is actually identical to a decoder with enable, as illustrated below:

Exercise: Provide the truth table for above demultiplexer.

2x4 Decoder

D

S1

S0

Y0 = D.S1'.S0'

Y1 = D.S1'.S0

Y2 = D.S1.S0'

Y3 = D.S1.S0E

Outline

Encoder

Demultiplexer

Multiplexer

Multiplexer IC Package

Multiplexer (1/5)

A multiplexer is a device which has (i) a number of input lines (ii) a number of selection lines (iii) one output line

It steers one of 2n inputs to a single output line, using n selection lines. Also known as a data selector.

2n:1Multiplexer outputinputs

:

select

...

Multiplexer (2/5)

Truth table for a 4-to-1 multiplexer:

mux Y

Inputs

select

S1 S0

I0

I1

I2

I3

I0 I1 I2 I3 S1 S0 Y

d0 d1 d2 d3 0 0 d0d0 d1 d2 d3 0 1 d1d0 d1 d2 d3 1 0 d2d0 d1 d2 d3 1 1 d3

S1 S0 Y

0 0 I00 1 I11 0 I21 1 I3

4:1MUX

Y

Inputs

select

S1 S0

I0

I1

I2

I3

0

1

2

3Output

Multiplexer (3/5)

Output of multiplexer is “sum of the (product of data lines and selection lines)”

Example: the output of a 4-to-1 multiplexer is:

Y = I0.(S1'.S0') + I1.(S1'.S0) + I2.(S1.S0') + I3.(S1.S0)

A 2n-to-1-line multiplexer, or simply 2n:1 MUX, is made from an n: 2n decoder by adding to it 2n input lines, one to each AND gate.

Multiplexer (4/5)

Four-to-one multiplexer design.

S1 S0

0 1 2 3

2-to-4 Decoder

I0

I1

I2

I3

Y

S1 S0

I0

I1

I2

I3

Y

Multiplexer (5/5)

An application:

Helps share a single communication line among a number of devices.

At any time, only one source and one destination can use the communication line.

Outline

Encoder

Demultiplexer

Multiplexer

Multiplexer IC Package

Multiplexer IC Package

Some IC packages have a few multiplexers in each package. The selection and enable inputs are common to all multiplexers within the package.

S (select)

A0

A1

A2

A3

B0

B1

B2

B3

E' (enable)

Y0

Y1

Y2

Y3

E’ S Output Y1 X all 0’s0 0 select A0 1 select B

Quadruple 2:1 multiplexer