Post on 23-Feb-2016
description
EEM 486: Computer Architecture
Designing Single Cycle Control
The Big Picture: Where are We Now?
Control
Datapath
Memory
ProcessorInput
Output
An Abstract View of the Implementation
DataOut
Clk
5
Rw Ra Rb32 32-bitRegisters
Rd
ALU
Clk
Data In
DataAddress Ideal
DataMemory
Instruction
InstructionAddress
IdealInstruction
Memory
Clk
PC
5Rs
5Rt
32
323232A
B
Nex
t Ad
dres
s
Control
Datapath
Control SignalsConditions
Recap: A Single Cycle Datapath We have everything except control signals (underline)
32
ALUctr
Clk
busW
RegWr
3232
busA
32busB
55 5Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Extender
Mux
Mux
3216imm16
ALUSrc
ExtOp
Mux
MemtoReg
Clk
Data InWrEn
32Adr
DataMemory
32
MemWrALU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel
Recap: Meaning of the Control Signals nPC_MUX_sel: 0 PC PC + 4
1 PC PC + 4 + SignExt(Im16) || 00
AdrInst
Memory
AdderAdder
PC
Clk
00Mux
4
nPC_MUX_sel
PC Extimm
16
Recap: Meaning of the Control Signals ExtOp: “zero”, “sign” ALUsrc: 0 regB; 1 immed ALUctr: “add”, “sub”, “or”
MemWr: 1 write memory
MemtoReg: 0 ALU; 1 Mem
RegDst: 0 “rt”; 1 “rd”
RegWr: 1 write register
32
ALUctr
Clk
busW
RegWr
3232
busA
32busB
55 5Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Extender
Mux
3216imm16
ALUSrcExtOp
Mux
MemtoReg
Clk
Data InWrEn32 Adr
DataMemory
MemWrALU
Equal
0
1
0
1
01
=
RTL: The Add Instruction
add rd, rs, rt
◦ mem[PC] Fetch the instruction from memory
◦ R[rd] R[rs] + R[rt] The actual operation
◦ PC PC + 4 Calculate the next instruction’s address
op rs rt rd shamt funct061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
Instruction Fetch Unit at the Beginning of Add
Fetch the instruction from Instruction memory: Instruction mem[PC]
Same for all instructions Adr
InstMemory
AdderAdder
PC
Clk
00Mux
4
nPC_MUX_selim
m16
Instruction<31:0>
0
1
The Single Cycle Datapath During Add R[rd] R[rs] + R[rt]
32
ALUctr = Add
Clk
busW
RegWr = 1
3232
busA
32busB
55 5Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = 1
Extender
Mux
Mux
3216imm16
ALUSrc=0
ExtOp = x
Mux
MemtoReg = 0
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr=0ALU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel= +4
Instruction Fetch Unit at the End of Add PC PC + 4
◦ This is the same for all instructions except: Branch and Jump
Adr
InstMemory
AdderAdder
PC
Clk
00Mux
4
nPC_MUX_sel
imm
16Instruction<31:0>
0
1
The Single Cycle Datapath During Or Immediate R[rt] R[rs] or ZeroExt[Imm16]
RegDst =
32
ALUctr =
Clk
busW
RegWr =
3232
busA
32busB
55 5Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
Rd
Extender
Mux
Mux
3216imm16
ALUSrc =
ExtOp =
Mux
MemtoReg =
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr = ALU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel =
The Single Cycle Datapath During Or Immediate
32
ALUctr = Or
Clk
busW
RegWr = 1
3232
busA
32busB
55 5Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = 0
Extender
Mux
Mux
3216imm16
ALUSrc = 1
ExtOp = 0
Mux
MemtoReg = 0
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr = 0
ALU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel= +4
The Single Cycle Datapath During Load R[rt] Data Memory [ R[rs] + SignExt[imm16] ]
32
ALUctr=Add
Clk
busW
RegWr = 1
3232
busA
32busB
55 5Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = 0
Extender
Mux
Mux
3216imm16
ALUSrc = 1
ExtOp = 1
Mux
MemtoReg = 1
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr = 0ALU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel= +4
The Single Cycle Datapath During Store Data Memory [ R[rs] + SignExt[imm16] ] R[rt]
32
ALUctr =
Clk
busW
RegWr =
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst=
Extender
Mux
Mux
3216imm16
ALUSrc =
ExtOp =
Mux
MemtoReg =
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr = ALU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<
21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel =
The Single Cycle Datapath During Store
32
ALUctr= Add
Clk
busW
RegWr = 0
3232
busA
32busB
55 5Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = x
Extender
Mux
Mux
3216imm16
ALUSrc = 1
ExtOp = 1
Mux
MemtoReg = x
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr = 1ALU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel= +4
The Single Cycle Datapath During Branch if (R[rs] - R[rt] == 0) then Zero 1 ; else Zero 0
32
ALUctr= Sub
Clk
busW
RegWr = 0
3232
busA
32busB
55 5Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = x
Extender
Mux
Mux
3216imm16
ALUSrc = 0
ExtOp = x
Mux
MemtoReg = x
Clk
Data InWrEn
32Adr
DataMemory
32
MemWr = 0ALU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel= “Br”
Instruction Fetch Unit at the End of Branch
What is encoding of nPC_sel?• Direct MUX select?• Branch / not branch
nPC_sel zero? MUX0 x 01 0 01 1 1
Instruction<31:0>nPC_sel Adr
InstMemory
AdderAdder
PC
Clk
00Mux
4
imm
16
0
1
Zero
nPC_MUX_sel
Step 4: Given Datapath: RTL Control
ALUctrRegDst ALUSrcExtOp MemtoRegMemWr Zero
Instruction<31:0><21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel
Adr
InstMemory
DATA PATH
Control
Op
<21:25>
Fun
RegWr
Summary of Control Signalsinst Register TransferADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4”SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4”ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4”LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4”STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rt]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4”BEQ if (R[rs] == R[rt]) then PC <– [PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = “Br”, ALUctr = “sub”
Logic For Each Control Signal nPC_sel <= if (OP == BEQ) then “Br” else “+4” ALUsrc <= if (OP == “Rtype”) then “regB” else
“immed” ALUctr <= if (OP == “Rtype”) then funct
elseif (OP == ORi) then “OR” elseif (OP ==
BEQ) then “sub” else “add”
ExtOp <= _____________ MemWr <= _____________ MemtoReg <= _____________ RegWr: <=_____________ RegDst: <= _____________
Logic for Each Control Signal nPC_sel <= if (OP == BEQ) then “Br” else “+4” ALUsrc <= if (OP == “Rtype”) then “regB” else
“immed” ALUctr <= if (OP == “Rtype”) then funct
elseif (OP == ORi) then “OR” elseif (OP == BEQ)
then “sub” else “add” ExtOp <= if (OP == ORi) then “zero” else “sign” MemWr <= (OP == Store) MemtoReg<= (OP == Load) RegWr: <= if ((OP == Store) || (OP == BEQ)) then 0 else 1 RegDst: <= if ((OP == Load) || (OP == ORi)) then 0 else 1
Putting it All Together: A Single Cycle Processor
32
ALUctr
Clk
busW
RegWr
3232
busA
32busB
55 5Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Extender
Mux
Mux
3216imm16
ALUSrc
ExtOp
Mux
MemtoReg
Clk
Data InWrEn
32Adr
DataMemory
32
MemWrALU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
MainControlop 6
ALUControlfunc
6
3ALUop
ALUctr3RegDst
ALUSrc:
Instr<5:0>
Instr<31:26>
Instr<15:0>
nPC_sel
Recap: An Abstract View of the Critical Path (Load)
Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew
Clk
5
Rw Ra Rb32 32-bitRegisters
RdALU
Clk
Data In
DataAddress Ideal
DataMemory
Instruction
InstructionAddress
IdealInstruction
Memory
Clk
PC
5Rs
5Rt
16Imm
32
323232A
B
Nex
t Ad
dres
s
Worst Case Timing (Load)
Clk
PC
Rs, Rt, Rd,Op, Func
Clk-to-Q
ALUctr
Instruction Memory Access Time
Old Value New Value
RegWr Old Value New Value
Delay through Control Logic
busARegister File Access Time
Old Value New Value
busBALU Delay
Old Value New Value
Old Value New Value
New Value
Old Value
ExtOp Old Value New Value
ALUSrc Old Value New Value
MemtoReg
Old Value New Value
Address Old Value New Value
busW Old Value New
Delay through Extender & Mux
RegisterWrite Occurs
Data Memory Access Time
Drawback of this Single Cycle ProcessorLong cycle time:
◦ Cycle time must be long enough for the load instruction:PC’s Clock -to-Q +Instruction Memory Access Time +Register File Access Time +ALU Delay (address calculation) +Data Memory Access Time +Register File Setup Time +Clock Skew
Cycle time for load is much longer than needed for all other instructions
Single cycle datapath => CPI=1, CCT => long 5 steps to design a processor
1. Analyze instruction set => datapath requirements2. Select set of datapath components & establish clock methodology3. Assemble datapath meeting the requirements4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic
Control is the hard part MIPS makes control easier
• Instructions same size• Source registers always in same place• Immediates same size, location• Operations always on registers/immediates
Summary
Control
Datapath
Memory
ProcessorInput
Output