Post on 26-Mar-2018
EEET0413VLSI Design and ToolsLecture7: Sequential Logics
Asst.Prof.Dr. Amorn Jiraseree-amornkun
Electronic Department,
Mahanakorn University of Technology
ReadingsRabaey, Chapter 7.
Goals of This ChapterImplementation techniques for
Register: latches and flipflopsSchmitt TriggersOscillator, pulse generators
Static versus Dynamic RealizationClocking Strategies
Storage Mechanisms
Positive Feedback Charge-Based
COMBINATIONALLOGIC
Inputs Outputs
Next stateCurrent State
Q DState
Register
CLOCK
Sequential Logic
STATIC DYNAMIC
Static vs Dynamic StorageStatic storage
preserve state as long as the power is onhave positive feedback (regeneration) with an internalconnection between the output and the inputuseful when updates are infrequent (clock gating)
Dynamic storagestore state on parasitic capacitorsonly hold state for short periods of time (milliseconds)require periodic refreshusually simpler, so higher speed and lower power
Latches vs FlipflopsLatches (with Clock)
level sensitive circuit that passes inputs to Q when the clock ishigh (or low) - transparent modeinput sampled on the falling edge of the clock is held stablewhen clock is low (or high) - hold mode
Flipflops (edge-triggered)edge sensitive circuits that sample the inputs on a clocktransition
positive edge-triggered: 0 1negative edge-triggered: 1 0
built using latches (e.g., master-slave flipflops)
Vi2 Vo2Vo1Vi1
Cascaded Inverters
A
Vi1 = Vo2
B
C
Review: The Regenerative PropertySmall deviation from biaspoint C (e.g., from noise)is amplified andregenerated around thecircuit loop until eitherpoint A or B is reachedIf the gain in the transientregion is larger than 1,only A and B are stableoperation points. C is ametastable operationpoint.
Review: Bistable CircuitsThe cross-coupling of twoinverters results in a bistablecircuit (a circuit with twostable states)Have to be able to change the stored value by making A(or B) temporarily unstable by increasing the loop gain to avalue larger than 1
done by applying a trigger pulse at Vi1 or Vi2
the width of the trigger pulse need to be only a little largerthan the total propagation delay around the loop circuit(twice the delay of an inverter)
Vi1
Vi2
Review: SR Latch
S R Q !Q Action0 0 Q !Q memory1 0 1 0 set0 1 0 1 reset1 1 0 0 disallowed
S
RQ
!Q
Review: Clocked D Latch
clock
QD
clock
D
Q
!Q
clock
transparent mode
hold mode
In our courseAll latches meanclocked latches
D
Clk
Q D
Clk
Q
Flipflopstores data whenclock rises (falls)
Clk
D
Q
Clk
D
Q
Latches versus Flipflops IILatchstores data whenclock is high (low)
Positive and Negative Latches
In
Out
Clk
OutStable
OutFollow In
OutStable
OutFollow In
D QG
In Out
Clk
Positive Latch
In
Out
Clk
OutStable
OutFollow In
OutStable
OutFollow In
D QG
In Out
Clk
Negative Latch
• N latch is transparentwhen = 0
• P latch is transparentwhen = 1
Latch-Based Design
NLatch
PLatchLogic
Logic
clock
Out outputstable
outputstable
time
clock
In datastable
time
time
tsu thold
tc-q
Timing Metrics
Timing DefinitionsSetup time, tsetup is the time that the data inputs (D)must be valid before the clock transition
0 to 1 transition for a positive edge-triggered device1 to 0 transition for a negative edge-triggered device
Hold time, thold is the time that the data inputs mustremain valid after the clock edgePropagation Delay, tc-q is the worst case propagationdelay (with reference to the clock edge)
time to copy D to Q
T tc-q + tplogic + tsutcdreg + tcdlogic thold
T (clock period)
System Timing Constraints
COMBINATIONALLOGIC
Inputs Outputs
Next stateCurrent State
Q DState
Register
CLOCKtcd: contamination delay = minimum delay
Notes on System Timing ConstraintsIt is important to minimize the values of the timingparameters associated with the register.In modern high-performance systems, the registerpropagation delay and set-up times account for a significantportion of the clock period.
DEC Alpha EV6 has a maximum logic depth of 12 gates andthe register overhead accounts for about 15% of the clockperiod.
Hold time becomes an issue when there is little logic betweenregisters or when the clocks at different registers aresomewhat out of phase due to clock skew.
D
CLK
CLK
D
can implement as NMOS-only PT
Building A (Static) Latch
CLK
CLK
CLK
D
Q
Cutting the feedback loop(Mux-based latch)
Overpowering the feedback loop(as in Static RAM)
For a latch, use the clock as a decoupling signal, that distinguishesbetween the transparent and opaque states
Q = !clk & Q | clk & DQ = clk & Q | !clk & D
Negative Latch
QD
clk
0
1
feedback
transparent when theclock is low
Change the stored value by cutting the feedback loop
MUX Based Latches
Positive Latch
QD
clk
1
0
feedback
transparent when theclock is high
!clk
clk
input sampled(transparent mode)
feedback(hold mode)
TG MUX Based Latch Implementation
Q
D
clk
clk
!clk
Positive Latch
clk load is two transistors (and twofor !clk) = clock load of 4Having to generate both clk and !clk(nonoverlapping clocks)
QD
clk !Q
!clkReduced clock load, butthreshold drop at output of passtransistors so reduced noisemargins and performance
PT MUX Based Latch Implementation
!clk
clk
input sampled(transparent mode)
feedback(hold mode)
clk
QM
Q
D
clk
QD
clk = 0 transparent hold
clk = 1 hold transparent
0
1 Q1
0
D
clk
Q
clk
SlaveMaster
QM
Master Slave Based ET Flipflop
T1
T2 Q
D
clk
QM
I1
I2 I3
I4
I5 I6
T3
T4
Master Slave
!clkclk
master transparentslave hold
master holdslave transparent
20 Transistors*8 clock loads
* Ignore clk buffer
MS ET Implementation
Assume propagation delays are tpd_inv and tpd_tx, that thecontamination delay is 0, and that the inverter delay to derive!clk is 0Set-up time - time before rising edge of clk that D must bevalid
Propagation delay - time for QM to reach Q
Hold time - time D must be stable after rising edge of clk
MS ET Timing Properties
tsu = 3 * tpd_inv + tpd_tx
tpd = tpd_inv + tpd_tx
thold = 0
Notes on MS ET Timing PropertiesSet-up time
How long before the rising edge does D have to be stablesuch that QM samples the value reliably?D has to propagate through I1, T1, I3 and I2 before therising edge to ensure that the node voltages on bothterminals of T2 are the same value.
Propagation delay timeSince the delay of I2 is included in the set-up time, theoutput of I4 is valid before the rising edge of clk, so thedelay is simply the delay through T3 and I6
Hold timesince T1 turns off when the clock goes high, any changesin D after clk goes high are not seen, so hold time is 0
Set-up Time Simulation
D clk
QM
I2 out
tsetup = 0.21 ns
works correctly
Volts
Time (ns)
-0.5
0
0.5
1
1.5
2
2.5
3
0 0.2 0.4 0.6 0.8 1
Q
Set-up Time Simulation II
-0.5
0
0.5
1
1.5
2
2.5
3
0 0.2 0.4 0.6 0.8 1
Volts
Time (ns)
D clk
QM
I2 out
tsetup = 0.20 ns
Q
the clock is enabled before the nodes on both sidesof the transmission gate T2 settle to the same value
Fails!
Reduced Load MS ET FF
!clkclk
QD
!clk clk
I1
I2 I4
I3
QM T2
T1
Clock load per register is important since it directly impactsthe power dissipation of the clock network.Can reduce the clock load (at the cost of robustness) bymaking the circuit ratioed
to switch the state of the master, T1 must be sized tooverpower I2to avoid reverse conduction, I4 must be weaker than I1
reverse conduction
12 Transistors4 clock loads
S
QR
Q
Cross-coupled NANDs
This is not used in datapaths any more,but is a basic building block for memory cell
Overpowering The Feedback LoopClocked SR Latch
S R
clkclk
M1
M2
M3
M4
M5
M6
M7
M8
clkclk
SR
M1
M2
M3
M4
M5M6 S
R
clk
clk
6 Transistor CMOS SR Latch
6 Transistors2 Clock loads
Problems with noisemargins and staticpower consumption dueto threshold drop acrosspass transistorsOnce again, sizing isimportant - especiallyM5 and M6
Review: Storage Mechanisms
D
CLK
CLK
Q
Dynamic(charge-based)
CLK
CLK
CLK
D
Q
Static(Positive Feedback)
Useful when update is infrequent Simpler, Faster, and Lower Power
!clk clk
T1 T2I1 I2 QQM
D
C1
C2clk !clk
!clk
clk
master transparentslave hold
master holdslave transparent
master slave
tsu =thold =tc-q =
tpd_txzero2 tpd_inv + tpd_tx
Dynamic ET Flipflop8 Transistors4 Clock loads
clk2
clk1tnon_overlap
master transparentslave hold
master holdslave transparent
Dynamic Two-Phase ET FFclk1 clk2
T1 T2I1 I2 Q
QM
D
C1
C2!clk1 !clk2
Pseudostatic Dynamic LatchRobustness considerations limit the use of dynamic FF’s
Coupling between signal nets and internal storage nodes can injectsignificant noise and destroy the FF stateLeakage currents cause state to leak away with timeInternal dynamic nodes don’t track fluctuations in VDD that reducesnoise margins
A simple fix is to make the circuit pseudostaticclk
T1D
!clk
Slight increase in delay(adds to the capacitiveload) and powerconsumption, but itimproves noise immunitysignificantly
Non-Bistable Sequential CircuitsPreviously, we have defined a circuit having twostable states a bi-stable circuitOther regenerative circuits, which are non-bistable:
MonostableOnly one stable state -> Pulse generators, One-shotcircuits
AstableNo stable states -> Oscillator, On-chip clock generator
Schmitt TriggerA special regenerative circuit exhibiting hysteresis inVTC.
In Out
Schmitt TriggerNon-Bistable Sequential Circuits
Vin
Vout VOH
VOL
VM– VM+
2 important propertiesHysteresisFast TransitionTime at the output
Noise Suppression using Schmitt Trigger
VIN
t0 t
VM+
VM-
VOUT
tt0 + tp
Example: Switch Debouncer
CMOS Schmitt Trigger
M1
M4M2
M3
VIN VOUTX
VDDMoves switchingthreshold of thefirst inverter
Adapting the ratio between PMOS and NMOS, depending upon thedirection of the transition results in a shift in switching threshold
Low-to-Highreff = kM1/(kM2 + kM4)
High-to-Lowreff = (kM1 + kM3)/kM2
Schmitt Trigger Simulated VTC
2.5
VM-
VM+
Vin (V)
2.0
1.5
1.0
0.5
0.00.0 0.5 1.0 1.5 2.0 2.5
Vx(V
)
2.5
k = 2k = 3
k = 4
k = 1
Vin (V)
2.0
1.5
1.0
0.5
0.00.0 0.5 1.0 1.5 2.0 2.5
Vx(V
)
Effect of varying the ratio of the PMOSdevice M4
Voltage Transfer Characteristics withhysteresis
M1 = 1 m/0.25 m, M2 = 3 m/0.25 m, M3 = 0.5 m/0.25 mM4 = 1.5 m/0.25 m M4 = k x 0.5 m/0.25 m
CMOS Schmitt Trigger (2)How does the gate operate?
M2
VIN VOUT
XM1
M5
M6M3
M4
Sketch VTC and find expression for VM- and VM+
Review: Ring Oscillator
0.0
0.0
0.5
1.0
1.5
2.0
2.5V1 V3 V5
3.0
20.50.5
time (ns)
Vol
ts
1.0 1.5
Period: T = 2 x tp x N
tp
Different Clock Duty-Cyclesand phases can be derivedusing simple logic operations
In
VDD
M3
M1
M2
M4
M5
VDD
M6
Vcontr Current starved inverter
Iref Iref
Schmitt Triggerrestores signal slopes
Voltage Controller Oscillator (VCO)Oscillation frequency of a VCO is a function (typicallynonlinear) of a control voltage
Delay of a current starved inverter depends on the currentlimit available to discharge the load capacitance of the gate
Current-Starved Inverter Simulation
0.5 1.5 2.5Vcontr (V)
0.0
2
4
6
t pH
L(n
sec)
Vctrl (V)
t pH
L(n
sec)
The device is in thesubthreshold regionwhen Vctrl is smallerthan VT, resulting inlarge variations of tpas the drive current isexponentiallydependent on thedrive voltage
Delay sensitive tonoise andvariation in Vctrl
Differential Delay Element and VCO
two stage VCO
v1
v2
v3
v4
- Inverting Inputs/Outputs+ Non-Inverting Inputs/Outputs
Oscillator with even numberof stages can be implemented
in2
Vctrl
Vo2 Vo1
in1
delay cell
+
+
-
-
Differential-type VCO has better immunity to common modenoise (e.g., supply noise) but consume more power
2-Stage VCO Simulation
0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
2 0.51.5
V 1 V 2 V 3 V 4
time (ns)2.5 3.5
The In-Phase and Quadrature Phase are produced simultaneously