Post on 05-Aug-2020
EEC 116 Lecture #9:Coping With Interconnect
Rajeevan AmirtharajahUniversity of California, Davis
Amirtharajah, EEC 116 Fall 2011 2
Announcements
• Lab 5 continues this week
• Homework 5 due Nov. 18
• Midterm curve being determined, will be posted shortly
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Outline
• Review: Wire Models
• Minimum Delay Sizing
• Wires: Rabaey Ch. 4 and Ch. 9 (Kang & Leblebici, 6.5-6.6)
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Wire Models
• Ideal Short Circuit
• Lumped Capacitor (C)
• Lumped RC
• Distributed RC
– Ladder Filter (series R, shunt C)
• Distributed LC
– Lossless Transmission Line (series L, shunt C)
• Distributed RLGC
– Lossy Transmission Line (series L, R; shunt G, C)
Com
plexity
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Interconnect Models: Regions of Applicability• For highest speed applications, wire must be treated as
a transmission line– Includes distributed series resistance, inductance,
capacitance, and shunt conductance (RLGC) • Many applications it is sufficient to use lumped
capacitance (C) or distributed series resistance-capacitance model (RC)
• Valid model depends on ratio of rise/fall times to time-of-flight along wire – l: wire length– v: propagation velocity (speed of light)– l/v: time-of-flight on wire
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Interconnect Models: Regions of Applicability
• Transmission line modeling (inductance significant):
trise (tfall) < 2.5 x (l / v)
• Either transmission line or lumped modeling:
2.5 x (l / v) < trise (tfall) < 5 x (l / v)
• Lumped modeling:
trise (tfall) > 5 x (l / v)
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Resistance• Resistance proportional to length and inversely
proportional to cross section
• Depends on material constant resistivity ρ (Ω-m)
t
W
L
WLR
tWL
ALR sq===
ρρt
Rsqρ
=
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Parallel-Plate Capacitance• Width large compared to dielectric thickness, height
small compared to width: E field lines orthogonal to substrate
tW
L
WLh
C rε=
hsubstrate
dielectric
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Total Capacitance Model
• Total capacitance per unit length is parallel-plate (area) term plus fringing-field term:
• Model is simple and works fairly well (Rabaey, 2nd ed.)
– More sophisticated numerical models also available
• Process models often give both area and fringing (also known as sidewall) capacitance numbers per unit length of wire for each interconnect layer
( )12log2
2 ++⎟
⎠⎞
⎜⎝⎛ −=+=
thtW
hccc rr
fringeppπεε
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RC Ladder Network Delay
• Elmore delay approximation for RC ladder network:
C/N
R/N
C/N
R/N …
C/N
R/N
NNRCRCRC
N
iiii
N
i
i
jjiiDi 2
111 1
+=== ∑∑ ∑
== =
τ
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RC Ladder Network Delay
• Elmore delay approximation for RC ladder network:
C/N
R/N
C/N
R/N …
C/N
R/N
22
2rcLRCtDN == ∞→Nas
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Distributed RC Model
• Differential equation at ith node (from KCL):
…
LrVVVV
tVLc iiiii
Δ−+−
=∂
∂Δ −+ )()( 11
LrΔ LrΔ LrΔ
LcΔ LcΔ LcΔ
inV outV1−iV iV
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Distributed RC Wire Step Response
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
0.5
1
1.5
2
2.5
time (nsec)
volta
ge (
V)
x= L/10
x = L/4
x = L/2
x= L
Source: Digital Integrated Circuits, 2nd ©
half way down wire
end of wire
1/10 of the way down wire
time
• Step-response of an RC Wire as a function of time and space (Fig. 4-15, p. 157)
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Intrinsic (Self-Load) and Extrinsic Capacitance
wireCgC iC
gC
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RC Switch Model for Inverter Sizing
wireCiC
gCgwireext CCC +=
eqR
• Model delay using ideal switch and resistor for MOSFET
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Unloaded Inverter Delay• Estimate delay using ideal switch and resistor model
(RC time constant):
• Define intrinsic inverter delay (with fudge factor):
• Ci consists of source / drain and overlap capacitance
( )extiqepd CCRt +∝
( )iextiqe CCCR +∝ 1
( )iextp0 CCt +∝ 1
iqep0 CRt 69.0=
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Fastest Loaded Inverter Sizing • Decrease delay by enlarging transistor (increases
current, decreases Req) by factor S:
• Intrinsic delay independent of sizing• Infinite S yields fastest gate (eliminates external load),
reducing delay to intrinsic in the limit
⎟⎟⎠
⎞⎜⎜⎝
⎛+=
i
exti
qepd SC
CSCS
Rt 169.0
⎟⎟⎠
⎞⎜⎜⎝
⎛+=
i
extppd SC
Ctt 10
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Relating Self-Load to Gate Capacitance • Increasing transistor sizing enlarges self-load and gate
input capacitance• Convenient to relate them by a constant factor γ (γ
around 1 in submicron processes)
• f is effective fanout of gate• Delay depends only on ratio between external load
capacitance and input capacitance
( )γγ
ftC
Ctt pg
extppd +=⎟
⎟⎠
⎞⎜⎜⎝
⎛+= 11 00
gi CC γ=
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Inverter Chain Sizing for Minimum Delay
1gL FCC =1gC
• Using inverter sizing, want to minimize delay of driving large load CL
• Optimize using equivalent resistance delay equation derived in previous slides
1 2 N
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Total Inverter Chain Delay • Delay of the jth inverter stage is (ignoring wiring):
• Total delay is:
where
⎟⎟⎠
⎞⎜⎜⎝
⎛+=⎟
⎟⎠
⎞⎜⎜⎝
⎛+= +
γγj
pjg
jgpjpd
ft
CC
tt 11 0,
1,0,
∑∑=
+
=⎟⎟⎠
⎞⎜⎜⎝
⎛+==
N
j jg
jgp
N
jjpdpd C
CttT
1 ,
1,0
1, 1
γ
1,1, gLNg FCCC ==+
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Optimal Inverter Sizing for Minimum Delay • Minimize delay by taking partial derivatives wrt Cg,j , set
them equal to 0– N-1 equations in N unknowns– Solution for jth inverter is geometric mean of its
neighbors sizing:
• Implies each inverter has constant scale-up factor fj:
• Minimum delay:
1,1,, +−= jgjgjg CCC
NNgLj FCCff === 1,
( )γNppd FNtT += 10
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Optimal Inverter Stages for Minimum Delay • Delay trade off in the number of stages N
– Too many stages, intrinsic delay term dominates– Too few stages, extrinsic delay term due to fanout ratio
dominates
• Taking derivative of Tpd wrt N and setting equal to zero yields equation to solve for scale up factor for optimal number of stages:
0ln=−+
NFFF
NNγ
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Optimal Inverter Stages for Minimum Delay • Taking derivative of Tpd wrt N and setting equal to zero
yields scale up factor for optimal number of stages:
• Closed form solution when ,
• For more typical case of ,
• Often choose
⎟⎟⎠
⎞⎜⎜⎝
⎛+
= fefγ1
0=γ )ln(FN =71828.2== ef
6.3=f1=γ
4=f
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Long Interconnect Delay
• Calculate delay by applying Elmore delay expression and switch RC model for driving inverter
rw,cw,L
intC fanC
inV outV
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Long Interconnect Delay
• Plugging in:
– Rdr: driver resistance– Cint: driver intrinsic capacitance– Rw: total wire resistance– Cw: total wire capacitance– Cfan : input capacitance of fanout gate
fanwdr
wwdr
intdrpd
CRRCRR
CRt
)(69.0)38.069.0(
69.0
+++
+=
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Long Interconnect Delay
• Rearranging terms:
– Rdr: driver resistance– Cint: driver intrinsic capacitance– rw: per unit length wire resistance– cw: per unit length wire capacitance– Cfan : input capacitance of fanout gate
2)(38.0
)(69.0
)(69.0
Lcr
LCrcR
CCRt
ww
fanwwdr
fanintdrpd
++
++=
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Optimal Inverter Sizing for Delay Constraint • Problem: given a maximum propagation delay time
tp,max, find number of stages N and scaleup factor f s.t. overall area is minimized (i.e., find a solution that sets Tpd = tp,max
• Solve numerically using integer programming (see Figure 9-8, Rabaey p. 455)– N between 1 and 10 for F = 100-104 and tp,max/tp0
between 10 and 104
maxpN
ppd tFNtT ,/1
0 ≥=
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Driver Area for Delay Constraint Sizing• Driver area Adr can be derived as function of minimum
sized inverter area Amin:
• Summing the power series yields:
• Area inversely proportional to scaleup factor f
minN
dr AfffA )...1( 12 −++++=
minmin
N
dr AfFA
ffA
11
11
−−
=⎟⎟⎠
⎞⎜⎜⎝
⎛−−
=
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Driver Power for Delay Constraint Sizing• Driver power Pdr can be derived as function of minimum
sized inverter intrinsic capacitance Ci:
• Summing the power series yields:
• Power inversely proportional to scaleup factor f, but fdrconstrained by tp,max
drDDiN
dr fVCfffP 212 )...1( −++++=
drDDL
drDDidr fVfCfVC
fFP 22
111
−≈
−−
=
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Example
• Off-chip Capacitor Driver Sizing
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Long Transmission Gate Chain Delay
• Calculate delay for N transmission gates in series by applying Elmore delay expression and switch RC model for transmission gate
C C
inV outV
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Long Transmission Gate Chain Delay
• Elmore delay expression:
C C
inV outVeqR eqR
2)1(69.069.0
1
+== ∑
=
NNCRCR eq
N
keqDτ
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Buffered Transmission Gate Chain
• Insert buffers (inverters) every m transmission gates to reduce delay
C C
inV outV…
C
…m
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Buffered Transmission Gate Chain Delay
• Assume inverter has delay tinv inserted every mtransmission gates
• Plugging in:
• Buffering results in linear dependence on number of switches N instead of quadratic
inveqD
inveqD
tmNmNCR
tmNmmCR
mN
⎟⎠⎞
⎜⎝⎛ −+⎥⎦
⎤⎢⎣⎡ +
=
⎟⎠⎞
⎜⎝⎛ −+⎥⎦
⎤⎢⎣⎡ +
=
12
)1(69.0
12
)1(69.0
τ
τ
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Optimal Buffer Insertion for Minimum Delay
• Minimize delay by taking partial derivative wrt m, set equal to 0:
• Buffer insertion period depends on ratio of inverter delay and transmission gate switch RC delay
• Find minimum delay by plugging in mopt
CRtmeq
invopt 7.1=
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Minimum Buffered Transmission Gate Delay
• Geometric mean dependence should look familiar!7.12
7.169.0
17.1
2
17.1
69.0
12
)1(69.0
eqinveqinvD
inv
eq
inv
eq
inv
eqD
invopt
opteqD
CRtNCRtN
t
CRt
NCRtN
CR
tmNmN
CR
+⎥⎦⎤
⎢⎣⎡≈
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−+
⎥⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢⎢
⎣
⎡
⎟⎟⎠
⎞⎜⎜⎝
⎛+
=
⎟⎟⎠
⎞⎜⎜⎝
⎛−+⎥
⎦
⎤⎢⎣
⎡ +=
τ
τ
τ
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Buffered Long Wire
• Insert inverters (repeaters) m times in a long wire of total resistance R and total capacitance C
• Assume inverters have delay tinv, wire of length Land per unit length resistance r and capacitance c
• Find optimum number of repeaters mopt as above
mC /
inV outVmR /
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Optimal Repeater Insertion for Minimum Delay
• Minimize delay by taking partial derivative wrt m, set equal to 0:
• twire is delay of unbuffered wire• Corresponding minimum delay by plugging in mopt
• Optimal delay found when each wire segment delay equals inverter delay
inv
wire
invopt t
tt
rcLm ==38.0
invwireD tt2=τ
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Long Interconnect Delay With Repeater Size
• Taking optimal repeater sizing (S) into account:
– Rdr: minimum-sized driver resistance– Cdr: minimum-sized driver intrinsic capacitance– rw: per unit length wire resistance– cw: per unit length wire capacitance
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⎟⎠⎞
⎜⎝⎛+⎟
⎠⎞
⎜⎝⎛
+⎥⎦⎤
⎢⎣⎡ ++
= 2
)(38.0)(69.0
69.0
mLcrSC
mLr
SCm
LcCSS
R
m
wwdrw
drw
drdr
D
γτ
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Optimal Repeater Design for Minimum Delay
• Minimize delay in usual fashion:
• tp0(1+1/γ) is delay of fanout of 1 (f = 1) inverter
)/11()1(69.038.0
0 γγ +=
+=
p
wire
drdr
wwopt t
tCR
crLm
wwdrdrD crCRL)102.138.1( γτ ++=
drw
wdropt Cr
cRS =
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Optimal Repeater Design for Minimum Delay
• Inserting repeaters linearizes delay dependence on length
• Optimal wire segment length exists for given technology and interconnect layer (Critical Length Lcrit):
• Delay of a segment of critical length:
ww
p
optcrit cr
tm
LL38.0
)/11(0 γ+==
)/11()1(38.0
69.012 0, γγ
ττ +⎟⎟⎠
⎞⎜⎜⎝
⎛
++== p
opt
DcritD t
m
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Pipelined Long Wire
• If minimum delay is longer than clock cycle (which can be the case for global wires), then registers can be inserted to pipeline the wire
• Latency increases or stays the same, but throughput of wire increases
• One of many architecture-level options for long wires
mC /
inV outVmR /
Φ Φ
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Power Distribution Network Resistance
• Finite resistance of power/ground lines (total resistance R) causes voltage drops which degrade noise margins:
ΔV < Vout < VDD-ΔV
inV outVR
R
I
IX
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Single Layer Power Grid
• Power routed vertically or horizontally on same layer
• VDD/GND brought in from two edges of chip
• Local power grids strapped to this grid and routed to lower metal layers
Amirtharajah, EEC 116 Fall 2011 45
Dual Layer Power Grid
• Power routed vertically and horizontally on two layers
• VDD/GND brought in from all four edges of chip
• Local power grids strapped to this grid and routed to lower metal layers
• Can occupy 90% of two layers
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Power Planes
• Devote two layers to power
• VDD/GND brought in from all four edges of chip
• Drastically reduces power supply resistance
• Can shield signal layers from crosstalk
• Need enough layers for routing
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Power Distribution Bypass Capacitance
• Local supply bypass capacitance provides low impedance path for high frequency (switching) currents to flow, reducing drops on output voltage
inV outVR
R
I
IX C
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Next Topic: Memories
• Memory principles and circuits
– ROM: Read Only Memory
– RWM (Read/Write Memory) or RAM (Random Access Memory)
• DRAM, SRAM
– Nonvolatile memories (Flash, PROM, EEPROM)